findcos.vhd

来自「这是我的毕业设计」· VHDL 代码 · 共 49 行

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-- Company: 
-- Engineer:
--
-- Create Date:    09:27:38 10/05/07
-- Design Name:    
-- Module Name:    findcos - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.sincos.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity findcos is
	  Port ( addr : in std_logic_vector(7 downto 0);
           clk : in std_logic;
           cosout :out std_logic_vector(5 downto 0));
end findcos;

architecture Behavioral of findcos is

begin
  process(addr,clk) 	
  	
  begin
    if clk'event and clk='1' then 
        cosout<=cosvalue1(conv_integer(addr)); 
	  end if;  
  
  end process;


end Behavioral;