findsin.vhd

来自「这是我的毕业设计」· VHDL 代码 · 共 52 行

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-- Company: 
-- Engineer:
--
-- Create Date:    09:25:55 10/05/07
-- Design Name:    
-- Module Name:    findsin - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.sincos.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity findsin is
  Port ( clk : in std_logic;
           addr : in std_logic_vector(7 downto 0);           
           sinout : out std_logic_vector(5 downto 0)
           );

end findsin;

architecture Behavioral of findsin is

begin
 process(addr,clk) 	
 begin
  	if clk'event and clk='1' then         
  	    sinout<=sinvalue1(conv_integer(addr)); 
	end if;    
 end process;


end Behavioral;