📄 swepfre.twr
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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -ise d:\rfid\rfid_re\rfid_re.ise -intstyle ise -e 3
-l 3 -s 11 -xml swepfre swepfre.ncd -o swepfre.twr swepfre.pcf
Design file: swepfre.ncd
Physical constraint file: swepfre.pcf
Device,speed: xc4vsx55,-11 (ADVANCED 1.52 2005-01-22, STEPPING level 0)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk40 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
sin_out<0> | 7.168(R)|clk120_OBUF | 0.000|
sin_out<1> | 8.003(R)|clk120_OBUF | 0.000|
sin_out<2> | 7.982(R)|clk120_OBUF | 0.000|
sin_out<3> | 7.524(R)|clk120_OBUF | 0.000|
sin_out<4> | 7.736(R)|clk120_OBUF | 0.000|
sin_out<5> | 7.745(R)|clk120_OBUF | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk40
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk40 | 3.937| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
clk40 |clk120 | 4.177|
---------------+---------------+---------+
Analysis completed Fri Oct 05 14:46:25 2007
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Peak Memory Usage: 215 MB
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