finsin.vhd

这是我的毕业设计

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    19:38:41 09/30/07
-- Design Name:    
-- Module Name:    finsin - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.sincos.all
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity finsin is
 Port ( clk : in std_logic;
           addr : in std_logic_vector(7 downto 0);           
           sinout : out std_logic_vector(5 downto 0)
           );
end finsin;

architecture Behavioral of finsin is

begin
 process(addr,clk) 	
 begin
  	if clk'event and clk='1' then         
  	    sinout<=sinvalue(conv_integer(addr)); 
	end if;    
 end process;


end Behavioral;