and2_gate.map.summary

来自「这是用Verilog HDL编好的2选一数据选择器 可以直接使用 没有密码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Tue Apr 01 16:12:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : and2_gate
Top-level Entity Name : and2_gate
Family : Cyclone
Total logic elements : 1
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge