and2_gate.tan.qmsg

这是用Verilog HDL编好的2选一数据选择器 可以直接使用 没有密码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 01 16:12:38 2008 " "Info: Processing started: Tue Apr 01 16:12:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off and2_gate -c and2_gate --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off and2_gate -c and2_gate --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a c 8.679 ns Longest " "Info: Longest tpd from source pin \"a\" to destination pin \"c\" is 8.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns a 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'a'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { a } "NODE_NAME" } } { "and2_gate.v" "" { Text "F:/我的文档/学习文档/EDA技术/实验/Verilog/and2_gate/and2_gate.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.437 ns) + CELL(0.101 ns) 5.837 ns c~0 2 COMB LC_X1_Y2_N2 1 " "Info: 2: + IC(4.437 ns) + CELL(0.101 ns) = 5.837 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; COMB Node = 'c~0'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.538 ns" { a c~0 } "NODE_NAME" } } { "and2_gate.v" "" { Text "F:/我的文档/学习文档/EDA技术/实验/Verilog/and2_gate/and2_gate.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(1.879 ns) 8.679 ns c 3 PIN PIN_23 0 " "Info: 3: + IC(0.963 ns) + CELL(1.879 ns) = 8.679 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'c'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.842 ns" { c~0 c } "NODE_NAME" } } { "and2_gate.v" "" { Text "F:/我的文档/学习文档/EDA技术/实验/Verilog/and2_gate/and2_gate.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.279 ns ( 37.78 % ) " "Info: Total cell delay = 3.279 ns ( 37.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 62.22 % ) " "Info: Total interconnect delay = 5.400 ns ( 62.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "8.679 ns" { a c~0 c } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "8.679 ns" { a {} a~out0 {} c~0 {} c {} } { 0.000ns 0.000ns 4.437ns 0.963ns } { 0.000ns 1.299ns 0.101ns 1.879ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 16:12:39 2008 " "Info: Processing ended: Tue Apr 01 16:12:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}