and2_gate.fit.rpt

这是用Verilog HDL编好的2选一数据选择器 可以直接使用 没有密码

; ASDO,nCSO                                    ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+---------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                       ;
+--------------------------------------------------------------------------------+------------+
; Name                                                                           ; Value      ;
+--------------------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff         ;
; Mid Wire Use - Fit Attempt 1                                                   ; 0          ;
; Mid Slack - Fit Attempt 1                                                      ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                                            ; 2          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 2          ;
; LAB Count - Fit Attempt 1                                                      ; 2          ;
; Outputs per Lab - Fit Attempt 1                                                ; 0.500      ;
; Inputs per LAB - Fit Attempt 1                                                 ; 1.000      ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000      ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:2        ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:2        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2        ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2        ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2        ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2        ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:2        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:2        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:2        ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2        ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:2        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2        ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:2        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                                  ; 0          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0          ;
; LABs with Chains - Fit Attempt 1                                               ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0          ;
; Time - Fit Attempt 1                                                           ; 0          ;
+--------------------------------------------------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Placement                       ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff         ;
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000      ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Routing                         ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Peak Regional Wire - Fit Attempt 1 ; 0          ;
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Apr 01 16:12:33 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off and2_gate -c and2_gate
Info: Selected device EP1C3T100C7 for design "and2_gate"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 4 of 4 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C3T100I7 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/我的文档/学习文档/EDA技术/实验/Verilog/and2_gate/and2_gate.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Tue Apr 01 16:12:34 2008
    Info: Elapsed time: 00:00:01


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/我的文档/学习文档/EDA技术/实验/Verilog/and2_gate/and2_gate.fit.smsg.