fifotb.v

异步FIFO verilog实现 异步FIFO verilog实现

// testbench of fifo.v
//date:2005/6/3
//the file name:fifotb.v
//-----------------------------------------------------
module test_fifo;
    reg clk;
    reg rstp;
    reg[15:0] din;
    reg readp;
    reg writep;
    wire[15:0] dout;
    wire emptyp;
    wire fullp;
    wire[15:0] value;
    
    
    //instantiation
    fifo U1(.clk(clk),.rstp(rstp),.din(din),.readp(readp),.writep(writep)
             ,.dout(dout),.emptyp(emptyp),.fullp(fullp));
    
    
    //define read_word task,read date from fifo         
    task read_word;
        begin
            @(negedge clk);
            readp=1;
            @(posedge clk) #5;
            $display("Read %0h from FIFO",dout);
            readp=0;
        end
endtask


//define write_word task,write date to  fifo
task write_word;
    input [15:0] value;
    begin
        @(negedge clk);
        din=value;
        writep=1;
        @(posedge clk);
        $display("Write %0h to FIFO",din);
        #5;
        din=16'hzzzz;
        writep=0;
    end
endtask


//generate clock signal
initial
begin
    clk=0;
    forever
    begin
        #10 clk=1;
        #10 clk=0;
    end
end

initial
begin
    $shm_open("./fifo.shm");
    $shm_probe(test_fifo,"AS");
    
    //call test1 task,
      test1;
    $shm_close;
    $stop;
    
  
end
    
    task test1;
        begin
            din=16'bzzzz;
            writep=0;
            readp=0;
            
            rstp=1;
            #50;
            rstp=0;
            #50;
            
            write_word(16'h1111);
            write_word(16'h2222);
            write_word(16'h3333);
            
            read_word;
            read_word;
            
            write_word(16'h4444);
            
            //read a set value
            repeat(6)
            begin
                read_word;
            end
            
            //write a set date
            write_word(16'h0001);
            write_word(16'h0002);
            write_word(16'h0003);
            write_word(16'h0004);
            write_word(16'h0005);
            write_word(16'h0006);
            write_word(16'h0007);
            write_word(16'h0008);
          
          //read a set value
          repeat(6)
          begin
              read_word;
          end
          
          $display("Done TEST1.");
      end
  endtask
  
  always@(fullp)
  $display("fullp-%0b",fullp);
  
  always@(emptyp)
  $display("emmtyp=%0b",emptyp);
  
  always@(U1.head)
  $display("head=%0h",U1.head);
  
  always@(U1.tail)
  $display("tail=%0h",U1.tail);
  
  endmodule