pd2.v

digital phase_division Verilog

module pd2 ( In_0 , In_1 , Out_0 , Out_1 ) ;

input  In_0 ,  In_1 ;
output Out_0 , Out_1 ;

wire   T_In_0,T_In_1 ;
wire   T_F0_0,T_F0_1,T_F1_0,T_F1_1 ;
wire   T_U ;


assign T_In_0 = ~ ( In_0 & Out_1 ) ;
assign T_In_1 = ~ ( In_1 & Out_0 ) ;


lpm_ff lpm_ff_c_0 ( .aclr ( T_U ), .clock ( 1'b0 ), .data ( 1'bx ), .aset ( ~ T_In_0 ),.q ( T_F0_0 ) ) ;

defparam
        lpm_ff_c_0.LPM_WIDTH = 1 ,
        lpm_ff_c_0.LPM_FFTYPE = "DFF" ;


lpm_ff lpm_ff_c_1 ( .aclr ( T_U ), .clock ( 1'b0 ), .data ( 1'bx ), .aset ( ~ T_In_1 ),.q ( T_F1_0 ) ) ;

defparam
        lpm_ff_c_1.LPM_WIDTH = 1 ,
        lpm_ff_c_1.LPM_FFTYPE = "DFF" ;


assign T_U = ~ ( T_In_0 & T_In_1 & T_F0_0 & T_F1_0) ;


assign Out_0 = ~ ( T_In_0 & T_F0_0 & T_U ) ;
assign Out_1 = ~ ( T_In_1 & T_F1_0 & T_U ) ;


endmodule