pd4.v

来自「digital phase_division Verilog」· Verilog 代码 · 共 27 行

module pd4 ( In_0 , In_1 , Out_0 , Out_1 ) ;

input  In_0 ,  In_1 ;
output Out_0 , Out_1 ;

reg    Out_0 , Out_1 ;
wire   T_U;


always @( negedge In_0 or posedge T_U )
  if ( T_U )
    Out_0 = 1'b0 ;
  else
    Out_0 = 1'b1 ;


always @( negedge In_1 or posedge T_U )
  if ( T_U )
    Out_1 = 1'b0 ;
  else
    Out_1 = 1'b1 ;


assign T_U = Out_0 & Out_1 ;


endmodule