uart.map.eqn

VHDL编写的异步通信串行口设计用Quartus工具编译

--R1_FF[4] is TX:5|ShiftReg:$00007|FF[4]
--operation mode is normal

R1_FF[4]_lut_out = R1_FF[5];
R1_FF[4] = DFFEA(R1_FF[4]_lut_out, F6_dffs[0], !RESET, , C1L01Q, F11_dffs[4], !C1L7Q);


--R1_FF[5] is TX:5|ShiftReg:$00007|FF[5]
--operation mode is normal

R1_FF[5]_lut_out = R1_FF[6];
R1_FF[5] = DFFEA(R1_FF[5]_lut_out, F6_dffs[0], !RESET, , C1L01Q, F11_dffs[5], !C1L7Q);


--R1_FF[6] is TX:5|ShiftReg:$00007|FF[6]
--operation mode is normal

R1_FF[6]_lut_out = R1_FF[7];
R1_FF[6] = DFFEA(R1_FF[6]_lut_out, F6_dffs[0], !RESET, , C1L01Q, F11_dffs[6], !C1L7Q);


--R1_FF[7] is TX:5|ShiftReg:$00007|FF[7]
--operation mode is normal

R1_FF[7]_lut_out = GND;
R1_FF[7] = DFFEA(R1_FF[7]_lut_out, F6_dffs[0], !RESET, , C1L01Q, F11_dffs[7], !C1L7Q);


--C1L3 is TX:5|_~207
--operation mode is normal

C1L3 = RESET # C1L31Q # !C1L7Q;


--C1L4 is TX:5|_~209
--operation mode is normal

C1L4 = RESET # C1L11Q # !C1L7Q;


--RESET is RESET
--operation mode is input

RESET = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--Di[7] is Di[7]
--operation mode is input

Di[7] = INPUT();


--Di[6] is Di[6]
--operation mode is input

Di[6] = INPUT();


--Di[5] is Di[5]
--operation mode is input

Di[5] = INPUT();


--Di[4] is Di[4]
--operation mode is input

Di[4] = INPUT();


--Di[3] is Di[3]
--operation mode is input

Di[3] = INPUT();


--Di[2] is Di[2]
--operation mode is input

Di[2] = INPUT();


--Di[1] is Di[1]
--operation mode is input

Di[1] = INPUT();


--Di[0] is Di[0]
--operation mode is input

Di[0] = INPUT();


--Rx is Rx
--operation mode is input

Rx = INPUT();


--RCVD is RCVD
--operation mode is output

RCVD = OUTPUT(F21_dffs[0]);


--WR is WR
--operation mode is output

WR = OUTPUT(!P5_cout);


--SENT is SENT
--operation mode is output

SENT = OUTPUT(F31_dffs[0]);


--INT is INT
--operation mode is output

INT = OUTPUT(F41_dffs[0]);


--Tx is Tx
--operation mode is output

Tx = OUTPUT(!F7_dffs[0]);


--TXSTATUS is TXSTATUS
--operation mode is output

TXSTATUS = OUTPUT(F9_dffs[0]);


--TXSTART is TXSTART
--operation mode is output

TXSTART = OUTPUT(E1L3Q);


--TXEND is TXEND
--operation mode is output

TXEND = OUTPUT(C1L31Q);


--TXRESET is TXRESET
--operation mode is output

TXRESET = OUTPUT(RESET);


--TXCLK is TXCLK
--operation mode is output

TXCLK = OUTPUT(CLK);


--Do[7] is Do[7]
--operation mode is output

Do[7] = OUTPUT(F1_dffs[7]);


--Do[6] is Do[6]
--operation mode is output

Do[6] = OUTPUT(F1_dffs[6]);


--Do[5] is Do[5]
--operation mode is output

Do[5] = OUTPUT(F1_dffs[5]);


--Do[4] is Do[4]
--operation mode is output

Do[4] = OUTPUT(F1_dffs[4]);


--Do[3] is Do[3]
--operation mode is output

Do[3] = OUTPUT(F1_dffs[3]);


--Do[2] is Do[2]
--operation mode is output

Do[2] = OUTPUT(F1_dffs[2]);


--Do[1] is Do[1]
--operation mode is output

Do[1] = OUTPUT(F1_dffs[1]);


--Do[0] is Do[0]
--operation mode is output

Do[0] = OUTPUT(F1_dffs[0]);


--TXCFGREG[6] is TXCFGREG[6]
--operation mode is output

TXCFGREG[6] = OUTPUT(GND);


--TXCFGREG[5] is TXCFGREG[5]
--operation mode is output

TXCFGREG[5] = OUTPUT(VCC);


--TXCFGREG[4] is TXCFGREG[4]
--operation mode is output

TXCFGREG[4] = OUTPUT(VCC);


--TXCFGREG[3] is TXCFGREG[3]
--operation mode is output

TXCFGREG[3] = OUTPUT(GND);


--TXCFGREG[2] is TXCFGREG[2]
--operation mode is output

TXCFGREG[2] = OUTPUT(GND);


--TXCFGREG[1] is TXCFGREG[1]
--operation mode is output

TXCFGREG[1] = OUTPUT(GND);


--TXCFGREG[0] is TXCFGREG[0]
--operation mode is output

TXCFGREG[0] = OUTPUT(GND);


--TXDIVISOR[16] is TXDIVISOR[16]
--operation mode is output

TXDIVISOR[16] = OUTPUT(GND);


--TXDIVISOR[15] is TXDIVISOR[15]
--operation mode is output

TXDIVISOR[15] = OUTPUT(GND);


--TXDIVISOR[14] is TXDIVISOR[14]
--operation mode is output

TXDIVISOR[14] = OUTPUT(GND);


--TXDIVISOR[13] is TXDIVISOR[13]
--operation mode is output

TXDIVISOR[13] = OUTPUT(GND);


--TXDIVISOR[12] is TXDIVISOR[12]
--operation mode is output

TXDIVISOR[12] = OUTPUT(GND);


--TXDIVISOR[11] is TXDIVISOR[11]
--operation mode is output

TXDIVISOR[11] = OUTPUT(GND);


--TXDIVISOR[10] is TXDIVISOR[10]
--operation mode is output

TXDIVISOR[10] = OUTPUT(GND);


--TXDIVISOR[9] is TXDIVISOR[9]
--operation mode is output

TXDIVISOR[9] = OUTPUT(GND);


--TXDIVISOR[8] is TXDIVISOR[8]
--operation mode is output

TXDIVISOR[8] = OUTPUT(GND);


--TXDIVISOR[7] is TXDIVISOR[7]
--operation mode is output

TXDIVISOR[7] = OUTPUT(GND);


--TXDIVISOR[6] is TXDIVISOR[6]
--operation mode is output

TXDIVISOR[6] = OUTPUT(GND);


--TXDIVISOR[5] is TXDIVISOR[5]
--operation mode is output

TXDIVISOR[5] = OUTPUT(GND);


--TXDIVISOR[4] is TXDIVISOR[4]
--operation mode is output

TXDIVISOR[4] = OUTPUT(GND);


--TXDIVISOR[3] is TXDIVISOR[3]
--operation mode is output

TXDIVISOR[3] = OUTPUT(VCC);


--TXDIVISOR[2] is TXDIVISOR[2]
--operation mode is output

TXDIVISOR[2] = OUTPUT(VCC);


--TXDIVISOR[1] is TXDIVISOR[1]
--operation mode is output

TXDIVISOR[1] = OUTPUT(GND);


--TXDIVISOR[0] is TXDIVISOR[0]
--operation mode is output

TXDIVISOR[0] = OUTPUT(GND);


--TXREG[7] is TXREG[7]
--operation mode is output

TXREG[7] = OUTPUT(F11_dffs[7]);


--TXREG[6] is TXREG[6]
--operation mode is output

TXREG[6] = OUTPUT(F11_dffs[6]);


--TXREG[5] is TXREG[5]
--operation mode is output

TXREG[5] = OUTPUT(F11_dffs[5]);


--TXREG[4] is TXREG[4]
--operation mode is output

TXREG[4] = OUTPUT(F11_dffs[4]);


--TXREG[3] is TXREG[3]
--operation mode is output

TXREG[3] = OUTPUT(F11_dffs[3]);


--TXREG[2] is TXREG[2]
--operation mode is output

TXREG[2] = OUTPUT(F11_dffs[2]);


--TXREG[1] is TXREG[1]
--operation mode is output

TXREG[1] = OUTPUT(F11_dffs[1]);


--TXREG[0] is TXREG[0]
--operation mode is output

TXREG[0] = OUTPUT(F11_dffs[0]);


--XOUT[3] is XOUT[3]
--operation mode is output

XOUT[3] = OUTPUT(C1L31Q);


--XOUT[2] is XOUT[2]
--operation mode is output

XOUT[2] = OUTPUT(C1L61);


--XOUT[1] is XOUT[1]
--operation mode is output

XOUT[1] = OUTPUT(C1L51);


--XOUT[0] is XOUT[0]
--operation mode is output

XOUT[0] = OUTPUT(C1L41);