decoder.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;

entity Decoder is
	PORT(	 
		D		: in 	std_logic_vector(31 downto 0);
	    C		: out	std_logic_vector(2 downto 0);
	    flag	: out 	std_logic_vector(1 downto 0);	
		c3		: out 	std_logic;
		c4		: out 	std_logic;	
		c5		: out 	std_logic;
		c6		: out 	std_logic;
		c7		: out 	std_logic;
		c8		: out 	std_logic;
		c9		: out 	std_logic;
		c10		: out 	std_logic;
		c11		: out 	std_logic;
		c12		: out 	std_logic;
		c13		: out 	std_logic;
		c14		: out 	std_logic;
		c15		: out 	std_logic;
		c16		: out 	std_logic;
		c17		: out 	std_logic;
		c18		: out 	std_logic;
		c19		: out 	std_logic;
		c20		: out 	std_logic;
		c21		: out 	std_logic;
		c22		: out 	std_logic;
		c25		: out 	std_logic;
		c26		: out 	std_logic;
		c27		: out 	std_logic;
		c28		: out 	std_logic;
		dataout : out 	std_logic_vector(31 downto 0)	
		);
end Decoder ;

architecture a of Decoder is
begin
  process(D)
  begin
	if(D(0)='1')then
		c(0)<='1';
	end if;
	if(D(1)='1')then
		c(1)<='1';
	end if;

	if(D(2)='1')then
		c(2)<='1';
	end if;

	if(D(3)='1')then
		c3<='1';
	end if;

	if(D(4)='1')then
		c4<='1';
	end if;

	if(D(5)='1')then
		c5<='1';
	end if;

	if(D(6)='1')then
		c6<='1';
	end if;

	if(D(7)='1')then
		c7<='1';
	end if;

	if(D(8)='1')then
		c8<='1';
	end if;

	if(D(9)='1')then
		c9<='1';
	end if;

	if(D(10)='1')then
		c10<='1';
	end if;

	if(D(11)='1')then
		c11<='1';
	end if;
	if(D(12)='1')then
		c12<='1';
	end if;
	if(D(13)='1')then
		c13<='1';
	end if;
	if(D(14)='1')then
		c14<='1';
	end if;
	if(D(15)='1')then
		c15<='1';
	end if;
	if(D(16)='1')then
		c16<='1';
	end if;
	if(D(17)='1')then
		c17<='1';
	end if;
	if(D(18)='1')then
		c18<='1';
	end if;
	if(D(19)='1')then
		c19<='1';
	end if;
	if(D(20)='1')then
		c20<='1';
	end if;
	if(D(21)='1')then
		c21<='1';
	end if;
	if(D(24)='1')then
		flag(0)<='1';
	end if;
	if(D(23)='1')then
		flag(1)<='1';
	end if;

	if(D(22)='1')then
		c22<='1';
	end if;
	if(D(25)='1')then
		c25<='1';
	end if;
	if(D(26)='1')then
		c26<='1';
	end if;
	if(D(27)='1')then
		c27<='1';
	end if;
	if(D(28)='1')then
		c28<='1';
	end if;
 end process;
dataout<=D;
end a;