counter_reg.vhd

来自「用VHDL编的简易CPU」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter_Reg is
port(
	 EN_down,reset,clk:	in std_logic;
	 downto0: out std_logic;
	 counter: buffer std_logic_vector(4 downto 0)
	 );
end Counter_Reg;

architecture a of Counter_Reg is
begin
	downto0<='1' when counter="00000" else '0';
	process(clk)
	begin
		if(reset='1')then
			counter<="10000";
		elsif(clk'event and clk='1')then
			if(EN_down='1')then
			  counter<=counter-1;
			end if;
		end if;
	end process;
end a;