mbr_reg.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;

entity MBR_Reg is
	PORT(	 
		ACC_IN, RAM_IN		: in 	std_logic_vector(15 downto 0);
	    EN_ACC,READ_RAM,clk	: in	std_logic;
	    q					: out 	std_logic_vector(15 downto 0)
		--MBR70				: out 	std_logic_vector(7 downto 0);
		--MBR158				: out   std_logic_vector(7 downto 0)
		);
end MBR_Reg ;

architecture a of MBR_Reg is
begin
 	process(clk)
		begin										
		   if(clk'event and clk = '1')then
               if(READ_RAM='1')then
                  q<=RAM_IN;
				 -- MBR70<=RAM_IN(7 downto 0);
				  --MBR158<=RAM_IN(15 downto 8);
               elsif(EN_ACC='1')then
				  q<=ACC_IN;
               end if;
		   end if;
    end process;
end a;