counter_reg.fit

用VHDL编的简易CPU

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/21/2008 15:26:04      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "counter_reg"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "clk"                          : INPUT_PIN  = 1      ;
    "EN_down"                      : INPUT_PIN  = 42     ;
    "reset"                        : INPUT_PIN  = 2      ;
    "counter0"                     : OUTPUT_PIN = 24     ;
    "counter1"                     : OUTPUT_PIN = 22     ;
    "counter2"                     : OUTPUT_PIN = 25     ;
    "counter3"                     : OUTPUT_PIN = 64     ;
    "counter4"                     : OUTPUT_PIN = 21     ;
    "downto0"                      : OUTPUT_PIN = 23     ;
    "|LPM_ADD_SUB:56|addcore:adder|pcarry2" : LOCATION   = LC2_B10;
    ":5"                           : LOCATION   = LC4_B10;
    ":7"                           : LOCATION   = LC6_B10;
    ":9"                           : LOCATION   = LC8_B10;
    ":11"                          : LOCATION   = LC1_B10;
    ":13"                          : LOCATION   = LC5_B10;
    ":124"                         : LOCATION   = LC3_B10;

END;

INTERNAL_INFO "counter_reg"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD4P1   : LORAX = "1:FB4->LC4_B10,->LC6_B10,->LC8_B10,->LC1_B10,->LC5_B10|";
    OD3P42  : LORAX = "1:FB3|2:FH3R1,PA5R1C9->LC4_B10,->LC6_B10,->LC8_B10,->LC1_B10,->LC5_B10||";
    OD1P2   : LORAX = "1:FB1->LC4_B10,->LC6_B10,->LC8_B10,->LC1_B10,->LC5_B10|";
    LC4_B10 : LORAX = "1:MSW0R1C8,HHL21R1->OH8R1P21|";
    LC6_B10 : LORAX = "1:MSW6R1C8,G71R1->OH6R1P64|";
    LC8_B10 : LORAX = "1:MSW7R1C9,HHL27R1->OH15R1P25|";
    LC1_B10 : LORAX = "1:MSW1R1C8,G4R1->OH9R1P22|";
    LC5_B10 : LORAX = "1:MSW5R1C8,HHL45R1->OH13R1P24|";
    LC3_B10 : LORAX = "1:MSW3R1C8,HHL6R1->OH11R1P23|";
	LC2_B10 : LORAX2 = "X, LC8_B10, LC5_B10, LC1_B10";
	LC4_B10 : LORAX2 = "OD3P42, LC4_B10, LC6_B10, LC2_B10";
	LC6_B10 : LORAX2 = "X, OD3P42, LC6_B10, LC2_B10";
	LC8_B10 : LORAX2 = "OD3P42, LC8_B10, LC1_B10, LC5_B10";
	LC1_B10 : LORAX2 = "X, OD3P42, LC1_B10, LC5_B10";
	LC5_B10 : LORAX2 = "X, X, OD3P42, LC5_B10";
	LC3_B10 : LORAX2 = "X, LC4_B10, LC6_B10, LC2_B10";
END;