pc_reg.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity PC_Reg is
	PORT(  
		MBR_IN					: in 	std_logic_vector(7 downto 0);
	    EN_MBR,increase1,reset,clk	: in	std_logic;
	    PC					: buffer 	std_logic_vector(7 downto 0)
		);
end PC_Reg ;

architecture a of PC_Reg is
begin
 	process (clk)
		begin										
		    if(reset='1')then
                 PC<="00000000";   
            elsif(clk'event and clk = '1')then
                 if(EN_MBR='1')then
				      PC<=MBR_IN;
                 elsif(increase1='1')then
                      PC<=PC+1;
                 end if;
			end if;
	end process;
 end a;