car.vhd

来自「用VHDL编的简易CPU」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 

entity car is
	port(
	     cin: in std_logic_vector(7 downto 0);
	     add1,load,reset,clk: in std_logic;					
		 car: buffer std_logic_vector(7 downto 0)
		);
end car;

architecture a of car is
begin
	process(clk)
	  begin
		if(clk'event and clk='1')then
			if(reset='1')then
				car<="00000000";
			elsif(add1='1')then
				car<=car+1;
			elsif(load='1')then
				car<=cin;
			end if;
		end if;
	end process;
end a;