ram.hif

来自「用VHDL编的简易CPU」· HIF 代码 · 共 59 行

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	altram.tdf
	{
		altram [DEVICE_FAMILY,USE_EAB=ON,REGISTERINPUTMODE=DEFAULT,FILE=NO_FILE,NUMWORDS,AD_WIDTH,WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [memmodes.inc,lpm_decode.inc,lpm_mux.inc,aglobal.inc]
		{
			2 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=DATA,FILE="d:\cpu\ram.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8,Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data15,Data14,Data13,Data12,Data11,Data10,Data9,Data8,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
		}
	}
	lpm_ram_dq.tdf
	{
		lpm_ram_dq [DEVICE_FAMILY,LPM_FILE=NO_FILE,LPM_OUTDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS,LPM_WIDTHAD,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [altram.inc,lpm_mux.inc,lpm_decode.inc,aglobal.inc]
		{
			1 [DEVICE_FAMILY=FLEX10K,LPM_FILE="d:\cpu\ram.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_INDATA=REGISTERED,LPM_WIDTHAD=8,LPM_WIDTH=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,we,address0,address1,address2,address3,address4,address5,address6,address7,data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,data11,data12,data13,data14,data15,inclock];
		}
	}
	ram.gdf
	{
		ram [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	ram::(0,0):(0): ram.gdf
	{
		lpm_ram_dq::(0,0):(1): lpm_ram_dq.tdf
		{
			altram:2:(101,5):(70,sram): altram.tdf;
		}
	}
}