mr_reg.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity MR_Reg is
port(
	 MBR_In: in std_logic_vector(15 downto 0);
	 EN_MBR,shiftr,shiftr_in,clk: in std_logic;
	 MR: buffer std_logic_vector(15 downto 0)
	 --Q1: buffer std_logic
	 
	 );
end MR_Reg;

architecture a of MR_Reg is
--signal temp: std_logic;

begin
	process(clk)
		begin
		if(clk'event and clk='1')then
			if(EN_MBR='1')then
				MR<=MBR_In;
			elsif(shiftr='1')then
				--temp<=MR(0);
				MR<=shiftr_in&MR(15 downto 1);
				--Q1<=temp;
			--else Q1<=Q1;
				 
			end if;
		end if;
	end process;
end a;