mar_reg.vhd

来自「用VHDL编的简易CPU」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;

entity MAR_Reg is
 PORT(	 
	 PC_IN,MBR_IN	 : in std_logic_vector(7 downto 0);
	 EN_PC,EN_MBR,clk : in std_logic;
	 q				 : out std_logic_vector(7 downto 0)	
	  );
end MAR_Reg ;

architecture a of MAR_Reg is
begin
 	process(clk)
		begin										
		    if(clk'event and clk = '1')then
               if(EN_PC='1')then
				   q<= PC_IN;
               elsif(EN_MBR='1')then
                   q<=MBR_IN;
               end if;
			end if;
	end process;
end a;