ir_opcode.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;

entity IR_opcode is
	PORT(	 
		 MBR_IN				: in 	std_logic_vector(7 downto 0);
	     EN_opcode,clk		: in	std_logic;
	     opcode				: out 	std_logic_vector(7 downto 0)
		 );
	
end IR_opcode;

architecture a of IR_opcode is
begin
 		process(clk)
		begin										
		      if(clk'event and clk = '1')then
                 if(EN_opcode='1')then
                    opcode<=MBR_IN;
                    end if;
			      end if;
		end process;
 end a;