b_reg.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity B_Reg is
	PORT(  
		MBR_IN		: in 	std_logic_vector(15 downto 0);
	    EN_MBR,clk	: in	std_logic;
	    BR			: buffer 	std_logic_vector(15 downto 0)
		 );
end B_Reg ;

architecture a of B_Reg is
begin
 		process(clk)
			begin										
                  if(clk'event and clk = '1')then
                     if(EN_MBR='1')then
				      BR<= MBR_IN;
                     end if;
			      end if;
		    end process;
 end a;