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来自「verilog源代码 王金明教程用的配套代码和一些可综合代码」· 代码 · 共 28 行

# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl 
# reading C:\Modeltech_6.0\win32/../modelsim.ini
# reading modelsim.ini
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "E:/source/chap5/decode4_7.v" 
cd E:/source/chap5
# reading modelsim.ini
vlog -reportprogress 300 -work work E:/source/chap5/decode4_7.v
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module decode4_7
# 
# Top level modules:
# 	decode4_7
vlog -reportprogress 300 -work work D:/eda/led7s/led7s.v
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module led_7s
# ** Error: D:/eda/led7s/led7s.v(2): In, out, or inout does not appear in port list: A.
# ** Error: D:/eda/led7s/led7s.v(3): In, out, or inout does not appear in port list: led7s.