nrz_2_manchester.v

NRZ码到Manchester转换器 verilog

module NRZ_2_Manchester(B_out,B_in,clk,reset);
    output    B_out;
    input     B_in;
    input     clk,reset;
    reg       B_out;
    reg [1:0] state,next_state;
    
    parameter S_0 = 0,S_1 = 1,
              S_2 = 2,S_3 = 3;
              
    always @(negedge clk or negedge reset)
    if(reset == 0)state<=S_0;else state<=next_state;
    
    always @(state or B_in) begin
        B_out = 0;
        case(state)
            S_0:begin if(B_in == 0)next_state = S_1;else next_state = S_3;end
            S_1:begin next_state = S_2;end
            S_2:begin B_out = 1;if(B_in == 0)next_state = S_1;else next_state = S_3;end
            S_3:begin B_out = 1;next_state = S_0;end
        endcase
    end
    
endmodule

module stimulus();
    reg  CLK,RESET;
    reg  BIN;
    wire BOUT;
    
    NRZ_2_Manchester T1(
    .B_out(BOUT),
    .B_in(BIN),
    .clk(CLK),
    .reset(RESET)
    );
    
    initial
        $monitor($time," : IN = %b OUT = %b ", BIN,BOUT,);
    
    initial begin
           RESET <= 0;BIN <= 0;
        #5 if(BOUT != 0)
        $display($time," : Reset State_0  Failed ! ");
        RESET <= 1;
        #10 if(BOUT != 0)
        $display($time," : State_1 Failed ! "); 
        #5 BIN <= 1;
        #5 if(BOUT != 1)
        $display($time," : State_2 Failed ! ");
        #10 if(BOUT != 1)
        $display($time," : State_3 Failed ! "); 
        #45 BIN <= 0;
        #40 BIN <= 1;
        #20 BIN <= 0;
        #60 $stop;
        
    end
    
    initial
    begin
         CLK=1'b0;
         forever #5 CLK=~CLK;
    end
    
endmodule