full-adder.fit

5 bits 的加法器與減法器合併電路之原始程式製作

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 05/06/2007 07:30:02      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "full-adder"
BEGIN

    DEVICE = "EP610ILC-10";

    "Enable"                       : INPUT_PIN  = 27     ;
    "X"                            : INPUT_PIN  = 17     ;
    "Y"                            : INPUT_PIN  = 13     ;
    "Z"                            : INPUT_PIN  = 3      ;
    "CRAAY"                        : OUTPUT_PIN = 12     ; -- LC16
    "SUM"                          : OUTPUT_PIN = 10     ; -- LC15

END;