ddr_sdram_post_summary.txt

来自「nois 2cpu 硬件实现编程」· 文本 代码 · 共 20 行

NOTE:     Speed Grade c6 used for analysis
NOTE:     Memory device can operate at 85.00 MHz with a lower CL than 2.5
  
 DDR read data capture: DDR Data to DQS strobe edges at capture registers. 
             Setup slack is  1959 ps    associated with pin 'ddr_dq[4]'  ( variation port 'dq(12)', 'input_cell_H[0]')              
             Hold slack is   1680 ps    associated with pin 'ddr_dq[7]'  ( variation port 'dq(15)', 'input_cell_L[0]')              
  
 Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').  
             Setup slack is  3565 ps    associated with pin 'ddr_dq[7]'  ( variation port 'dq(15)', 'input_cell_L[0]')                  
             Hold slack is   3488 ps    associated with pin 'ddr_dq[7]'  ( variation port 'dq(7)', 'input_cell_H[0]')              
  
 Read Postamble Enable: Enable-release to DQS strobe postamble period at negative-edge capture registers.  
             Setup slack is  3482 ps    associated with pin 'ddr_dq[4]'  ( variation port 'dq(4)', 'input_cell_L[0]')                  
             Hold slack is    795 ps    associated with pin 'ddr_dq[3]'  ( variation port 'dq(3)', 'input_cell_H[0]')              
  
 Read Postamble Control: Preset-release ('dq_enable_reset') to DQS strobe negative edges at postamble register ('dq_enable').       
             Setup slack is  5304 ps    associated with pin 'ddr_dq[0]'  ( variation port 'dq(8)', 'input_cell_L[0]')                  
             Hold slack is   2011 ps    associated with pin 'ddr_dq[0]'  ( variation port 'dq(0)', 'input_cell_L[0]')