ask_dem_real.hif

baseband解调

PARAMETER_SIGNED_DEC
USR
CB
662
PARAMETER_SIGNED_DEC
USR
CC
776
PARAMETER_SIGNED_DEC
USR
CD
659
PARAMETER_SIGNED_DEC
USR
CE
656
PARAMETER_SIGNED_DEC
USR
CF
539
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
10
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_14_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_14_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(126).cnf
db|ask_dem_real.(126).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
126
PARAMETER_SIGNED_DEC
USR
C2
127
PARAMETER_SIGNED_DEC
USR
C3
253
PARAMETER_SIGNED_DEC
USR
C4
0
PARAMETER_SIGNED_DEC
USR
C5
126
PARAMETER_SIGNED_DEC
USR
C6
127
PARAMETER_SIGNED_DEC
USR
C7
253
PARAMETER_SIGNED_DEC
USR
C8
0
PARAMETER_SIGNED_DEC
USR
C9
126
PARAMETER_SIGNED_DEC
USR
CA
127
PARAMETER_SIGNED_DEC
USR
CB
253
PARAMETER_SIGNED_DEC
USR
CC
0
PARAMETER_SIGNED_DEC
USR
CD
126
PARAMETER_SIGNED_DEC
USR
CE
127
PARAMETER_SIGNED_DEC
USR
CF
253
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_0_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_1_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_2_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_3_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_4_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_5_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_6_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_7_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_8_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_9_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_10_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_11_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_12_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_13_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_0_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_1_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_2_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_3_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_4_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_5_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_6_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_7_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_8_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_9_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_10_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_11_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_12_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_13_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(127).cnf
db|ask_dem_real.(127).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
386
PARAMETER_SIGNED_DEC
USR
C2
385
PARAMETER_SIGNED_DEC
USR
C3
259
PARAMETER_SIGNED_DEC
USR
C4
0
PARAMETER_SIGNED_DEC
USR
C5
386
PARAMETER_SIGNED_DEC
USR
C6
385
PARAMETER_SIGNED_DEC
USR
C7
259
PARAMETER_SIGNED_DEC
USR
C8
0
PARAMETER_SIGNED_DEC
USR
C9
386
PARAMETER_SIGNED_DEC
USR
CA
385
PARAMETER_SIGNED_DEC
USR
CB
259
PARAMETER_SIGNED_DEC
USR
CC
0
PARAMETER_SIGNED_DEC
USR
CD
386
PARAMETER_SIGNED_DEC
USR
CE
385
PARAMETER_SIGNED_DEC
USR
CF
259
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur2_n_14_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur2_n_14_pp
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(128).cnf
db|ask_dem_real.(128).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
24
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_5_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_7_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_3_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_4_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_5_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_6_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_7_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_3_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_4_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_5_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_6_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_7_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_5_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_6_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_0_n_7_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_4_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_5_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_6_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_0_n_7_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_4_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_5_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_6_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_0_n_7_n
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(129).cnf
db|ask_dem_real.(129).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
25
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_3_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_2_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_1_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_1_n_3_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_2_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_1_n_3_n
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(130).cnf
db|ask_dem_real.(130).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
26
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_2_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_2_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_2_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_2_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_2_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_2_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_2_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_2_n_1_n
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(131).cnf
db|ask_dem_real.(131).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
27
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_1_lut_l_3_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_2_lut_l_3_n_0_n
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(132).cnf
db|ask_dem_real.(132).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
28
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_0_n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_1_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_0_n_1_n
}
# end
# entity
sadd_lpm_cen
# storage
db|ask_dem_real.(133).cnf
db|ask_dem_real.(133).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_lpm_cen.v
62aa4e6e1b65434bef7a771f690f887
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
29
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n
}
# end
# entity
mac_tl
# storage
db|ask_dem_real.(134).cnf
db|ask_dem_real.(134).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|mac_tl.v
f8dfa8ea226692edae9632f969a49b8
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
DATA_WIDTH
30
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|mac_tl:Umtl
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|mac_tl:Umtl
}
# end
# entity
par_ctrl
# storage
db|ask_dem_real.(135).cnf
db|ask_dem_real.(135).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|par_ctrl.v
878dfc0242d30e9bee11a611db8a3b7
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
REG_LEN
9
PARAMETER_SIGNED_DEC
USR
REG_BIT
4
PARAMETER_SIGNED_DEC
USR
CH_WIDTH
0
PARAMETER_SIGNED_DEC
USR
NUM_CH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|par_ctrl:Uctrl
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|par_ctrl:Uctrl
}
# end
# entity
lpm_mult1
# storage
db|ask_dem_real.(136).cnf
db|ask_dem_real.(136).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_mult1.vhd
ad61e4c4a447ffce9377a45c1575f4b
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_mult1:inst6
}
# end
# entity
lpm_mult
# storage
db|ask_dem_real.(137).cnf
db|ask_dem_real.(137).cnf
# case_insensitive
# source_file
..|..|..|quartus|libraries|megafunctions|lpm_mult.tdf
b667ddb4c1fb4f9df0f26e8c7fe21cf0
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
14
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHB
14
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHP
14
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHR
0
PARAMETER_UNKNOWN
DEF
LPM_WIDTHS
1
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
LUT
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_9ao
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
USE_AHDL_IMPLEMENTATION
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9