judge.vhd

来自「baseband解调」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity judge is
generic(code_period : integer :=99;
		half_code_period : integer :=49);--码元周期2

port(clk : in std_logic;
	data_in : in std_logic;
	data_out : out std_logic);
end judge;


architecture behave of judge is
--signal c : std_logic_vector(D downto 0);加一信号表示出错
signal count : integer range 0 to code_period;
signal start : integer range 0 to 51;
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			
			if start<half_code_period then
				if data_in='1' then
					start<=start+1;
				else
					start<=0;
				end if;
			elsif start=half_code_period then
				start<=half_code_period+1;
				count<=0;
--				flag<=0;
			elsif count=99 then
				count<=0;
				data_out<=data_in;
			else
				count<=count+1;	
			end if;		
			
		end if;
	end process;
end behave;