ask_dem_real.hif

baseband解调

3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|altsyncram_aof1:FIFOram
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|altsyncram_aof1:FIFOram
}
# end
# entity
cntr_bjb
# storage
db|ask_dem_real.(114).cnf
db|ask_dem_real.(114).cnf
# case_insensitive
# source_file
db|cntr_bjb.tdf
cb51e8ee392df495f1a6ea83e4350
6
# used_port {
sclr
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_bjb:rd_ptr_msb
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_bjb:rd_ptr_msb
}
# end
# entity
cntr_oj7
# storage
db|ask_dem_real.(115).cnf
db|ask_dem_real.(115).cnf
# case_insensitive
# source_file
db|cntr_oj7.tdf
19eefaf8c3eec94e645cb5cfa3887ae6
6
# used_port {
updown
-1
3
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_oj7:usedw_counter
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_oj7:usedw_counter
}
# end
# entity
cntr_cjb
# storage
db|ask_dem_real.(116).cnf
db|ask_dem_real.(116).cnf
# case_insensitive
# source_file
db|cntr_cjb.tdf
16c59830e6eee855a3d8b7efedd6b25d
6
# used_port {
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_cjb:wr_ptr
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo|cntr_cjb:wr_ptr
}
# end
# entity
auk_dspip_avalon_streaming_source
# storage
db|ask_dem_real.(117).cnf
db|ask_dem_real.(117).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
auk_dspip_avalon_streaming_source.vhd
a21f158f6c9ae54d6afa6f9d1adb577
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width_g
26
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
have_counter_g
false
PARAMETER_ENUM
USR
counter_limit_g
4
PARAMETER_SIGNED_DEC
USR
multi_channel_g
true
PARAMETER_ENUM
USR
 constraint(data)
25 downto 0
PARAMETER_STRING
USR
 constraint(data_count)
0 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_source_data)
25 downto 0
PARAMETER_STRING
USR
 constraint(at_source_channel)
0 downto 0
PARAMETER_STRING
USR
 constraint(at_source_error)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
auk_dspip_math_pkg.vhd
25746ad2295926525aa5743d99f3d3d
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_source:source
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_source:source
}
# end
# entity
auk_dspip_avalon_streaming_controller
# storage
db|ask_dem_real.(118).cnf
db|ask_dem_real.(118).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
auk_dspip_avalon_streaming_controller.vhd
281a4ffb76238a5caa5bc2a7256d61ae
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(sink_packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(source_packet_error)
1 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_controller:intf_ctrl
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_controller:intf_ctrl
}
# end
# entity
fir_I1_st
# storage
db|ask_dem_real.(119).cnf
db|ask_dem_real.(119).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_I1_st.v
ae55d862e973464f1d9d9ea8a4faab7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
DATA_WIDTH
14
PARAMETER_SIGNED_DEC
DEF
COEF_WIDTH
7
PARAMETER_SIGNED_DEC
DEF
ACCUM_WIDTH
26
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core
}
# end
# entity
tdl_da_lc
# storage
db|ask_dem_real.(120).cnf
db|ask_dem_real.(120).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|tdl_da_lc.v
308971e2fd5045b5e49bdf3185df66a
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WIDTH
14
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc0n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc1n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc2n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc3n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc4n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc5n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc6n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc7n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc8n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc9n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc10n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc11n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc12n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc13n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc14n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc15n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc16n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc17n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc18n
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|tdl_da_lc:Utdldalc19n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc0n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc1n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc2n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc3n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc4n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc5n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc6n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc7n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc8n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc9n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc10n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc11n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc12n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc13n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc14n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc15n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc16n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc17n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc18n
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|tdl_da_lc:Utdldalc19n
}
# end
# entity
sadd_cen
# storage
db|ask_dem_real.(121).cnf
db|ask_dem_real.(121).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|sadd_cen.v
194199dd33b3ca9f3d5948a3351d72
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IN_WIDTH
14
PARAMETER_SIGNED_DEC
USR
PIPE_DEPTH
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_0_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_1_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_2_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_3_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_4_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_5_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_6_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_7_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_8_sym_add
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|sadd_cen:U_9_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_0_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_1_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_2_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_3_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_4_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_5_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_6_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_7_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_8_sym_add
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|sadd_cen:U_9_sym_add
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(122).cnf
db|ask_dem_real.(122).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
100
PARAMETER_SIGNED_DEC
USR
C2
105
PARAMETER_SIGNED_DEC
USR
C3
205
PARAMETER_SIGNED_DEC
USR
C4
109
PARAMETER_SIGNED_DEC
USR
C5
209
PARAMETER_SIGNED_DEC
USR
C6
214
PARAMETER_SIGNED_DEC
USR
C7
314
PARAMETER_SIGNED_DEC
USR
C8
114
PARAMETER_SIGNED_DEC
USR
C9
214
PARAMETER_SIGNED_DEC
USR
CA
219
PARAMETER_SIGNED_DEC
USR
CB
319
PARAMETER_SIGNED_DEC
USR
CC
223
PARAMETER_SIGNED_DEC
USR
CD
323
PARAMETER_SIGNED_DEC
USR
CE
328
PARAMETER_SIGNED_DEC
USR
CF
428
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
10
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_0_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_1_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_2_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_3_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_4_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_5_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_6_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_7_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_8_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_9_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_10_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_11_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_12_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_13_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_0_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_1_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_2_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_3_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_4_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_5_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_6_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_7_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_8_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_9_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_10_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_11_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_12_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_13_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(123).cnf
db|ask_dem_real.(123).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
924
PARAMETER_SIGNED_DEC
USR
C2
919
PARAMETER_SIGNED_DEC
USR
C3
819
PARAMETER_SIGNED_DEC
USR
C4
915
PARAMETER_SIGNED_DEC
USR
C5
815
PARAMETER_SIGNED_DEC
USR
C6
810
PARAMETER_SIGNED_DEC
USR
C7
710
PARAMETER_SIGNED_DEC
USR
C8
910
PARAMETER_SIGNED_DEC
USR
C9
810
PARAMETER_SIGNED_DEC
USR
CA
805
PARAMETER_SIGNED_DEC
USR
CB
705
PARAMETER_SIGNED_DEC
USR
CC
801
PARAMETER_SIGNED_DEC
USR
CD
701
PARAMETER_SIGNED_DEC
USR
CE
696
PARAMETER_SIGNED_DEC
USR
CF
596
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
10
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur0_n_14_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur0_n_14_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(124).cnf
db|ask_dem_real.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
117
PARAMETER_SIGNED_DEC
USR
C2
120
PARAMETER_SIGNED_DEC
USR
C3
237
PARAMETER_SIGNED_DEC
USR
C4
123
PARAMETER_SIGNED_DEC
USR
C5
240
PARAMETER_SIGNED_DEC
USR
C6
243
PARAMETER_SIGNED_DEC
USR
C7
360
PARAMETER_SIGNED_DEC
USR
C8
125
PARAMETER_SIGNED_DEC
USR
C9
242
PARAMETER_SIGNED_DEC
USR
CA
245
PARAMETER_SIGNED_DEC
USR
CB
362
PARAMETER_SIGNED_DEC
USR
CC
248
PARAMETER_SIGNED_DEC
USR
CD
365
PARAMETER_SIGNED_DEC
USR
CE
368
PARAMETER_SIGNED_DEC
USR
CF
485
PARAMETER_SIGNED_DEC
USR
DATA_WIDTH
10
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_0_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_1_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_2_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_3_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_4_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_5_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_6_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_7_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_8_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_9_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_10_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_11_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_12_pp
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|fir_Q1_st:fir_core|rom_lut_r_cen:Ur1_n_13_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_0_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_1_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_2_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_3_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_4_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_5_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_6_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_7_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_8_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_9_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_10_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_11_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_12_pp
fir_I1:inst|fir_I1_new:fir_I1_new_inst|fir_I1_st:fir_core|rom_lut_r_cen:Ur1_n_13_pp
}
# end
# entity
rom_lut_r_cen
# storage
db|ask_dem_real.(125).cnf
db|ask_dem_real.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|ip|fir_compiler|lib|rom_lut_r_cen.v
bd2d9246d887c02de8932667ab03f
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
C0
0
PARAMETER_SIGNED_DEC
USR
C1
907
PARAMETER_SIGNED_DEC
USR
C2
904
PARAMETER_SIGNED_DEC
USR
C3
787
PARAMETER_SIGNED_DEC
USR
C4
901
PARAMETER_SIGNED_DEC
USR
C5
784
PARAMETER_SIGNED_DEC
USR
C6
781
PARAMETER_SIGNED_DEC
USR
C7
664
PARAMETER_SIGNED_DEC
USR
C8
899
PARAMETER_SIGNED_DEC
USR
C9
782
PARAMETER_SIGNED_DEC
USR
CA
779