ask_dem_real.hif

baseband解调

Version 6.1 Build 201 11/27/2006 SJ Full Version
11
869
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
..|..|..|ip|fir_compiler|lib|
..|..|..|ip|nco|lib|
..|..|..|ip|fft-v2.1.1|lib|
..|..|..|MegaCore|nco-v2.2.1|lib|
..|..|..|MegaCore|fir_compiler-v3.1.0|lib|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
fir_I1
# storage
db|ask_dem_real.(1).cnf
db|ask_dem_real.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fir_I1.v
6189632ad8a2a85cc84b1622eca691e7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
fir_I1:inst
}
# end
# entity
fir_I1_new
# storage
db|ask_dem_real.(2).cnf
db|ask_dem_real.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fir_I1_new.vhd
d7f2bcbac2d2925d36c4f2b88f8b2c4
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
auk_dspip_math_pkg.vhd
25746ad2295926525aa5743d99f3d3d
auk_dspip_lib_pkg.vhd
1434b72bd12b55dbe7d63e12f6e7d
}
# hierarchies {
fir_I1:inst|fir_I1_new:fir_I1_new_inst
}
# end
# entity
auk_dspip_avalon_streaming_sink
# storage
db|ask_dem_real.(3).cnf
db|ask_dem_real.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
auk_dspip_avalon_streaming_sink.vhd
fda3bacc6665638eead6e3a32796ce1
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width_g
14
PARAMETER_SIGNED_DEC
USR
packet_size_g
1
PARAMETER_SIGNED_DEC
USR
fifo_depth_g
5
PARAMETER_SIGNED_DEC
USR
min_data_count_g
2
PARAMETER_SIGNED_DEC
USR
pfc_mode_g
false
PARAMETER_ENUM
USR
sop_eop_calc_g
false
PARAMETER_ENUM
USR
family_g
Cyclone II
PARAMETER_STRING
USR
mem_type_g
Auto
PARAMETER_STRING
USR
 constraint(data)
13 downto 0
PARAMETER_STRING
USR
 constraint(packet_error)
1 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_data)
13 downto 0
PARAMETER_STRING
USR
 constraint(at_sink_error)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
auk_dspip_math_pkg.vhd
25746ad2295926525aa5743d99f3d3d
auk_dspip_lib_pkg.vhd
1434b72bd12b55dbe7d63e12f6e7d
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink
}
# end
# entity
scfifo
# storage
db|ask_dem_real.(4).cnf
db|ask_dem_real.(4).cnf
# case_insensitive
# source_file
..|..|..|quartus|libraries|megafunctions|scfifo.tdf
35622eb715ad7962dc948ede2925d2b
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
5
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
3
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
3
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
1
PARAMETER_SIGNED_DEC
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_1gd1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw0
-1
3
sclr
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
..|..|..|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
..|..|..|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
..|..|..|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
..|..|..|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
..|..|..|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
..|..|..|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo
}
# end
# entity
scfifo_1gd1
# storage
db|ask_dem_real.(5).cnf
db|ask_dem_real.(5).cnf
# case_insensitive
# source_file
db|scfifo_1gd1.tdf
3b2ae35cb176d9edddaefab29a15f5b
6
# used_port {
wrreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated
}
# end
# entity
a_dpfifo_6751
# storage
db|ask_dem_real.(6).cnf
db|ask_dem_real.(6).cnf
# case_insensitive
# source_file
db|a_dpfifo_6751.tdf
e9e4d03c99b6a24ab56b2d8264156f1
6
# used_port {
wreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo
fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_1gd1:auto_generated|a_dpfifo_6751:dpfifo
}
# end
# entity
altsyncram_aof1
# storage
db|ask_dem_real.(7).cnf
db|ask_dem_real.(7).cnf
# case_insensitive
# source_file
db|altsyncram_aof1.tdf
de28dfff66691f4d538632538191a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1