altsyncram_16q.tdf

baseband解调

			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a43 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a44 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 44,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 44,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a45 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 45,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 45,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a46 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 46,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 46,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a47 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 47,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 47,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a48 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 49,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 49,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[1..0]	: WIRE;
	address_b_wire[1..0]	: WIRE;

BEGIN 
	ram_block5a[48..0].clk0 = clock0;
	ram_block5a[48..0].clk1 = clock1;
	ram_block5a[48..0].ena0 = clocken0;
	ram_block5a[48..0].ena1 = clocken1;
	ram_block5a[0].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[1].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[2].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[3].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[4].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[5].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[6].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[7].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[8].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[9].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[10].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[11].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[12].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[13].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[14].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[15].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[16].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[17].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[18].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[19].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[20].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[21].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[22].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[23].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[24].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[25].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[26].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[27].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[28].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[29].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[30].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[31].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[32].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[33].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[34].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[35].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[36].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[37].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[38].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[39].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[40].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[41].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[42].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[43].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[44].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[45].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[46].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[47].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[48].portaaddr[] = ( address_a_wire[1..0]);
	ram_block5a[0].portadatain[] = ( data_a[0..0]);
	ram_block5a[1].portadatain[] = ( data_a[1..1]);
	ram_block5a[2].portadatain[] = ( data_a[2..2]);
	ram_block5a[3].portadatain[] = ( data_a[3..3]);
	ram_block5a[4].portadatain[] = ( data_a[4..4]);
	ram_block5a[5].portadatain[] = ( data_a[5..5]);
	ram_block5a[6].portadatain[] = ( data_a[6..6]);
	ram_block5a[7].portadatain[] = ( data_a[7..7]);
	ram_block5a[8].portadatain[] = ( data_a[8..8]);
	ram_block5a[9].portadatain[] = ( data_a[9..9]);
	ram_block5a[10].portadatain[] = ( data_a[10..10]);
	ram_block5a[11].portadatain[] = ( data_a[11..11]);
	ram_block5a[12].portadatain[] = ( data_a[12..12]);
	ram_block5a[13].portadatain[] = ( data_a[13..13]);
	ram_block5a[14].portadatain[] = ( data_a[14..14]);
	ram_block5a[15].portadatain[] = ( data_a[15..15]);
	ram_block5a[16].portadatain[] = ( data_a[16..16]);
	ram_block5a[17].portadatain[] = ( data_a[17..17]);
	ram_block5a[18].portadatain[] = ( data_a[18..18]);
	ram_block5a[19].portadatain[] = ( data_a[19..19]);
	ram_block5a[20].portadatain[] = ( data_a[20..20]);
	ram_block5a[21].portadatain[] = ( data_a[21..21]);
	ram_block5a[22].portadatain[] = ( data_a[22..22]);
	ram_block5a[23].portadatain[] = ( data_a[23..23]);
	ram_block5a[24].portadatain[] = ( data_a[24..24]);
	ram_block5a[25].portadatain[] = ( data_a[25..25]);
	ram_block5a[26].portadatain[] = ( data_a[26..26]);
	ram_block5a[27].portadatain[] = ( data_a[27..27]);
	ram_block5a[28].portadatain[] = ( data_a[28..28]);
	ram_block5a[29].portadatain[] = ( data_a[29..29]);
	ram_block5a[30].portadatain[] = ( data_a[30..30]);
	ram_block5a[31].portadatain[] = ( data_a[31..31]);
	ram_block5a[32].portadatain[] = ( data_a[32..32]);
	ram_block5a[33].portadatain[] = ( data_a[33..33]);
	ram_block5a[34].portadatain[] = ( data_a[34..34]);
	ram_block5a[35].portadatain[] = ( data_a[35..35]);
	ram_block5a[36].portadatain[] = ( data_a[36..36]);
	ram_block5a[37].portadatain[] = ( data_a[37..37]);
	ram_block5a[38].portadatain[] = ( data_a[38..38]);
	ram_block5a[39].portadatain[] = ( data_a[39..39]);
	ram_block5a[40].portadatain[] = ( data_a[40..40]);
	ram_block5a[41].portadatain[] = ( data_a[41..41]);
	ram_block5a[42].portadatain[] = ( data_a[42..42]);
	ram_block5a[43].portadatain[] = ( data_a[43..43]);
	ram_block5a[44].portadatain[] = ( data_a[44..44]);
	ram_block5a[45].portadatain[] = ( data_a[45..45]);
	ram_block5a[46].portadatain[] = ( data_a[46..46]);
	ram_block5a[47].portadatain[] = ( data_a[47..47]);
	ram_block5a[48].portadatain[] = ( data_a[48..48]);
	ram_block5a[48..0].portawe = wren_a;
	ram_block5a[0].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[1].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[2].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[3].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[4].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[5].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[6].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[7].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[8].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[9].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[10].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[11].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[12].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[13].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[14].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[15].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[16].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[17].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[18].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[19].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[20].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[21].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[22].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[23].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[24].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[25].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[26].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[27].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[28].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[29].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[30].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[31].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[32].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[33].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[34].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[35].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[36].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[37].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[38].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[39].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[40].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[41].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[42].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[43].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[44].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[45].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[46].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[47].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[48].portbaddr[] = ( address_b_wire[1..0]);
	ram_block5a[0].portbrewe = B"1";
	ram_block5a[1].portbrewe = B"1";
	ram_block5a[2].portbrewe = B"1";
	ram_block5a[3].portbrewe = B"1";
	ram_block5a[4].portbrewe = B"1";
	ram_block5a[5].portbrewe = B"1";
	ram_block5a[6].portbrewe = B"1";
	ram_block5a[7].portbrewe = B"1";
	ram_block5a[8].portbrewe = B"1";
	ram_block5a[9].portbrewe = B"1";
	ram_block5a[10].portbrewe = B"1";
	ram_block5a[11].portbrewe = B"1";
	ram_block5a[12].portbrewe = B"1";
	ram_block5a[13].portbrewe = B"1";
	ram_block5a[14].portbrewe = B"1";
	ram_block5a[15].portbrewe = B"1";
	ram_block5a[16].portbrewe = B"1";
	ram_block5a[17].portbrewe = B"1";
	ram_block5a[18].portbrewe = B"1";
	ram_block5a[19].portbrewe = B"1";
	ram_block5a[20].portbrewe = B"1";
	ram_block5a[21].portbrewe = B"1";
	ram_block5a[22].portbrewe = B"1";
	ram_block5a[23].portbrewe = B"1";
	ram_block5a[24].portbrewe = B"1";
	ram_block5a[25].portbrewe = B"1";
	ram_block5a[26].portbrewe = B"1";
	ram_block5a[27].portbrewe = B"1";
	ram_block5a[28].portbrewe = B"1";
	ram_block5a[29].portbrewe = B"1";
	ram_block5a[30].portbrewe = B"1";
	ram_block5a[31].portbrewe = B"1";
	ram_block5a[32].portbrewe = B"1";
	ram_block5a[33].portbrewe = B"1";
	ram_block5a[34].portbrewe = B"1";
	ram_block5a[35].portbrewe = B"1";
	ram_block5a[36].portbrewe = B"1";
	ram_block5a[37].portbrewe = B"1";
	ram_block5a[38].portbrewe = B"1";
	ram_block5a[39].portbrewe = B"1";
	ram_block5a[40].portbrewe = B"1";
	ram_block5a[41].portbrewe = B"1";
	ram_block5a[42].portbrewe = B"1";
	ram_block5a[43].portbrewe = B"1";
	ram_block5a[44].portbrewe = B"1";
	ram_block5a[45].portbrewe = B"1";
	ram_block5a[46].portbrewe = B"1";
	ram_block5a[47].portbrewe = B"1";
	ram_block5a[48].portbrewe = B"1";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block5a[48].portbdataout[0..0], ram_block5a[47].portbdataout[0..0], ram_block5a[46].portbdataout[0..0], ram_block5a[45].portbdataout[0..0], ram_block5a[44].portbdataout[0..0], ram_block5a[43].portbdataout[0..0], ram_block5a[42].portbdataout[0..0], ram_block5a[41].portbdataout[0..0], ram_block5a[40].portbdataout[0..0], ram_block5a[39].portbdataout[0..0], ram_block5a[38].portbdataout[0..0], ram_block5a[37].portbdataout[0..0], ram_block5a[36].portbdataout[0..0], ram_block5a[35].portbdataout[0..0], ram_block5a[34].portbdataout[0..0], ram_block5a[33].portbdataout[0..0], ram_block5a[32].portbdataout[0..0], ram_block5a[31].portbdataout[0..0], ram_block5a[30].portbdataout[0..0], ram_block5a[29].portbdataout[0..0], ram_block5a[28].portbdataout[0..0], ram_block5a[27].portbdataout[0..0], ram_block5a[26].portbdataout[0..0], ram_block5a[25].portbdataout[0..0], ram_block5a[24].portbdataout[0..0], ram_block5a[23].portbdataout[0..0], ram_block5a[22].portbdataout[0..0], ram_block5a[21].portbdataout[0..0], ram_block5a[20].portbdataout[0..0], ram_block5a[19].portbdataout[0..0], ram_block5a[18].portbdataout[0..0], ram_block5a[17].portbdataout[0..0], ram_block5a[16].portbdataout[0..0], ram_block5a[15].portbdataout[0..0], ram_block5a[14].portbdataout[0..0], ram_block5a[13].portbdataout[0..0], ram_block5a[12].portbdataout[0..0], ram_block5a[11].portbdataout[0..0], ram_block5a[10].portbdataout[0..0], ram_block5a[9].portbdataout[0..0], ram_block5a[8].portbdataout[0..0], ram_block5a[7].portbdataout[0..0], ram_block5a[6].portbdataout[0..0], ram_block5a[5].portbdataout[0..0], ram_block5a[4].portbdataout[0..0], ram_block5a[3].portbdataout[0..0], ram_block5a[2].portbdataout[0..0], ram_block5a[1].portbdataout[0..0], ram_block5a[0].portbdataout[0..0]);
END;
--VALID FILE