shift_taps_blg.tdf

baseband解调

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" NUMBER_OF_TAPS=1 TAP_DISTANCE=6 WIDTH=43 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 4.2 cbx_altdpram 2004:08:15:21:15:28:SJ cbx_altshift_taps 2004:08:15:21:15:58:SJ cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
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FUNCTION altsyncram_muu (address_a[1..0], address_b[1..0], clock0, clocken0, data_a[42..0], wren_a)
RETURNS ( q_b[42..0]);
FUNCTION cntr_3gc (clk_en, clock)
RETURNS ( cout, q[1..0]);

--synthesis_resources = lut 2 ram_bits (auto) 172 
SUBDESIGN shift_taps_blg
( 
	clock	:	input;
	shiftin[42..0]	:	input;
	shiftout[42..0]	:	output;
	taps[42..0]	:	output;
) 
VARIABLE 
	altsyncram2 : altsyncram_muu;
	cntr1 : cntr_3gc;
	clken	: NODE;

BEGIN 
	altsyncram2.address_a[] = cntr1.q[];
	altsyncram2.address_b[] = cntr1.q[];
	altsyncram2.clock0 = clock;
	altsyncram2.clocken0 = clken;
	altsyncram2.data_a[] = ( shiftin[]);
	altsyncram2.wren_a = B"1";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	shiftout[42..0] = altsyncram2.q_b[42..0];
	taps[] = altsyncram2.q_b[];
END;
--VALID FILE