altsyncram_muu.tdf

来自「baseband解调」· TDF 代码 · 共 1,396 行 · 第 1/4 页

TDF
1,396 行
字号
1234
	ram_block3a24 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a25 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a26 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a27 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a28 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a29 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a30 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a31 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a32 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 32,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 32,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a33 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 33,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 33,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a34 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 34,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 34,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a35 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a36 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 3,
			PORT_A_LOGICAL_RAM_DEPTH = 4,
			PORT_A_LOGICAL_RAM_WIDTH = 43,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock0",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 36,
			PORT_B_LAST_ADDRESS = 3,
			PORT_B_LOGICAL_RAM_DEPTH = 4,
			PORT_B_LOGICAL_RAM_WIDTH = 43,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1234

altsyncram_muu.tdf - 源码说明

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