📄 mux_fdb.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" LPM_SIZE=2 LPM_WIDTH=15 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 6.1 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ VERSION_END
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 15
SUBDESIGN mux_fdb
(
data[29..0] : input;
result[14..0] : output;
sel[0..0] : input;
)
VARIABLE
result_node[14..0] : WIRE;
sel_node[0..0] : WIRE;
w_data127w[1..0] : WIRE;
w_data141w[1..0] : WIRE;
w_data153w[1..0] : WIRE;
w_data165w[1..0] : WIRE;
w_data177w[1..0] : WIRE;
w_data189w[1..0] : WIRE;
w_data201w[1..0] : WIRE;
w_data213w[1..0] : WIRE;
w_data225w[1..0] : WIRE;
w_data237w[1..0] : WIRE;
w_data249w[1..0] : WIRE;
w_data261w[1..0] : WIRE;
w_data273w[1..0] : WIRE;
w_data285w[1..0] : WIRE;
w_data297w[1..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( ((sel_node[] & w_data297w[1..1]) # ((! sel_node[]) & w_data297w[0..0])), ((sel_node[] & w_data285w[1..1]) # ((! sel_node[]) & w_data285w[0..0])), ((sel_node[] & w_data273w[1..1]) # ((! sel_node[]) & w_data273w[0..0])), ((sel_node[] & w_data261w[1..1]) # ((! sel_node[]) & w_data261w[0..0])), ((sel_node[] & w_data249w[1..1]) # ((! sel_node[]) & w_data249w[0..0])), ((sel_node[] & w_data237w[1..1]) # ((! sel_node[]) & w_data237w[0..0])), ((sel_node[] & w_data225w[1..1]) # ((! sel_node[]) & w_data225w[0..0])), ((sel_node[] & w_data213w[1..1]) # ((! sel_node[]) & w_data213w[0..0])), ((sel_node[] & w_data201w[1..1]) # ((! sel_node[]) & w_data201w[0..0])), ((sel_node[] & w_data189w[1..1]) # ((! sel_node[]) & w_data189w[0..0])), ((sel_node[] & w_data177w[1..1]) # ((! sel_node[]) & w_data177w[0..0])), ((sel_node[] & w_data165w[1..1]) # ((! sel_node[]) & w_data165w[0..0])), ((sel_node[] & w_data153w[1..1]) # ((! sel_node[]) & w_data153w[0..0])), ((sel_node[] & w_data141w[1..1]) # ((! sel_node[]) & w_data141w[0..0])), ((sel_node[] & w_data127w[1..1]) # ((! sel_node[]) & w_data127w[0..0])));
sel_node[] = ( sel[0..0]);
w_data127w[] = ( data[15..15], data[0..0]);
w_data141w[] = ( data[16..16], data[1..1]);
w_data153w[] = ( data[17..17], data[2..2]);
w_data165w[] = ( data[18..18], data[3..3]);
w_data177w[] = ( data[19..19], data[4..4]);
w_data189w[] = ( data[20..20], data[5..5]);
w_data201w[] = ( data[21..21], data[6..6]);
w_data213w[] = ( data[22..22], data[7..7]);
w_data225w[] = ( data[23..23], data[8..8]);
w_data237w[] = ( data[24..24], data[9..9]);
w_data249w[] = ( data[25..25], data[10..10]);
w_data261w[] = ( data[26..26], data[11..11]);
w_data273w[] = ( data[27..27], data[12..12]);
w_data285w[] = ( data[28..28], data[13..13]);
w_data297w[] = ( data[29..29], data[14..14]);
END;
--VALID FILE
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