mult_n3o.tdf

baseband解调

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" DSP_BLOCK_BALANCING="Auto" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=18 LPM_WIDTHB=14 LPM_WIDTHP=32 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_mult 2004:10:14:16:46:16:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_padd 2004:10:28:17:00:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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--  party's intellectual property, are provided herein.


FUNCTION stratix_mac_mult (aclr[3..0], clk[3..0], dataa[17..0], datab[17..0], ena[3..0], signa, signb)
WITH ( 	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded) 
RETURNS ( dataout[35..0], scanouta[17..0], scanoutb[17..0]);
PARAMETERS
(
	dataout_width = 72
);
FUNCTION stratix_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[35..0], datab[35..0], datac[35..0], datad[35..0], ena[3..0], signa, signb, zeroacc)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_width,	datab_width,	datac_width,	datad_width,	dataout_width,	operation_mode,	output_clear,	output_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 2 
SUBDESIGN mult_n3o
( 
	dataa[17..0]	:	input;
	datab[13..0]	:	input;
	result[31..0]	:	output;
) 
VARIABLE 
	mac_mult2 : stratix_mac_mult
		WITH (
			dataa_width = 18,
			datab_width = 14
		);
	mac_out1 : stratix_mac_out
		WITH (
			dataa_width = 32,
			dataout_width = 72,
			operation_mode = "output_only"
		);
	aclr	: NODE;
	clken	: NODE;
	clock	: NODE;

BEGIN 
	mac_mult2.aclr[] = aclr;
	mac_mult2.clk[] = clock;
	mac_mult2.dataa[] = ( dataa[]);
	mac_mult2.datab[] = ( B"1111", datab[]);
	mac_mult2.ena[] = clken;
	mac_mult2.signa = B"1";
	mac_mult2.signb = B"1";
	mac_out1.aclr[] = aclr;
	mac_out1.clk[] = clock;
	mac_out1.dataa[] = ( B"0000", mac_mult2.dataout[31..0]);
	mac_out1.ena[] = clken;
	mac_out1.signa = B"1";
	mac_out1.signb = B"1";
	aclr = GND;
	clken = VCC;
	clock = GND;
	result[31..0] = mac_out1.dataout[31..0];
END;
--VALID FILE