fir_q.vhd

baseband解调

-- megafunction wizard: %FIR Compiler v3.1.0%

-- ============================================================
-- Megafunction Name(s):
-- 			fir_q_st
-- ============================================================
-- Generated by FIR Compiler 3.1.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
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-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY fir_Q IS
	PORT (
		clk	: IN STD_LOGIC;
		rst	: IN STD_LOGIC;
		data_in	: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
		fir_result	: OUT STD_LOGIC_VECTOR (43 DOWNTO 0);
		done	: OUT STD_LOGIC;
		rdy_to_ld	: OUT STD_LOGIC
	);
END fir_Q;

ARCHITECTURE SYN OF fir_Q IS


	COMPONENT fir_q_st
	PORT (
		clk	: IN STD_LOGIC;
		rst	: IN STD_LOGIC;
		data_in	: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
		fir_result	: OUT STD_LOGIC_VECTOR (43 DOWNTO 0);
		done	: OUT STD_LOGIC;
		rdy_to_ld	: OUT STD_LOGIC
	);

	END COMPONENT;

BEGIN

	fir_q_st_inst : fir_q_st
	PORT MAP (
		clk  =>  clk,
		rst  =>  rst,
		data_in  =>  data_in,
		fir_result  =>  fir_result,
		done  =>  done,
		rdy_to_ld  =>  rdy_to_ld
	);


END SYN;


-- =========================================================
-- FIR Compiler Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
-- 
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-- =========================================================