ask_dem_real.fit.smsg

baseband解调

        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:06
Info: Estimated most critical path is register to register delay of 12.803 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X36_Y14; Fanout = 2; REG Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|dffe66'
    Info: 2: + IC(1.121 ns) + CELL(0.517 ns) = 1.638 ns; Loc. = LAB_X37_Y16; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[7]~51'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.718 ns; Loc. = LAB_X37_Y16; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[8]~53'
    Info: 4: + IC(0.098 ns) + CELL(0.080 ns) = 1.896 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[9]~55'
    Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.976 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[10]~57'
    Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 2.056 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[11]~59'
    Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 2.136 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[12]~61'
    Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 2.216 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[13]~63'
    Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 2.296 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[14]~65'
    Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 2.376 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[15]~67'
    Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 2.456 ns; Loc. = LAB_X37_Y15; Fanout = 1; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[16]~69'
    Info: 12: + IC(0.000 ns) + CELL(0.458 ns) = 2.914 ns; Loc. = LAB_X37_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add153_result[17]~70'
    Info: 13: + IC(1.403 ns) + CELL(0.495 ns) = 4.812 ns; Loc. = LAB_X34_Y13; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add149_result[19]~83'
    Info: 14: + IC(0.000 ns) + CELL(0.458 ns) = 5.270 ns; Loc. = LAB_X34_Y13; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|add149_result[20]~84'
    Info: 15: + IC(1.059 ns) + CELL(0.517 ns) = 6.846 ns; Loc. = LAB_X35_Y15; Fanout = 2; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|op_1~426'
    Info: 16: + IC(0.000 ns) + CELL(0.458 ns) = 7.304 ns; Loc. = LAB_X35_Y15; Fanout = 5; COMB Node = 'lpm_mult4:inst14|altsquare:altsquare_component|altsquare_nva:auto_generated|op_1~427'
    Info: 17: + IC(1.072 ns) + CELL(0.495 ns) = 8.871 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'mod_judge:inst5|Add4~353'
    Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 8.951 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'mod_judge:inst5|Add4~355'
    Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 9.031 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'mod_judge:inst5|Add4~357'
    Info: 20: + IC(0.000 ns) + CELL(0.458 ns) = 9.489 ns; Loc. = LAB_X34_Y16; Fanout = 1; COMB Node = 'mod_judge:inst5|Add4~358'
    Info: 21: + IC(0.733 ns) + CELL(0.177 ns) = 10.399 ns; Loc. = LAB_X33_Y16; Fanout = 1; COMB Node = 'mod_judge:inst5|p[7]~572'
    Info: 22: + IC(0.155 ns) + CELL(0.521 ns) = 11.075 ns; Loc. = LAB_X33_Y16; Fanout = 3; COMB Node = 'mod_judge:inst5|p[7]~573'
    Info: 23: + IC(0.132 ns) + CELL(0.544 ns) = 11.751 ns; Loc. = LAB_X33_Y16; Fanout = 7; COMB Node = 'mod_judge:inst5|p[7]~576'
    Info: 24: + IC(0.294 ns) + CELL(0.758 ns) = 12.803 ns; Loc. = LAB_X33_Y16; Fanout = 3; REG Node = 'mod_judge:inst5|p[6]'
    Info: Total cell delay = 6.736 ns ( 52.61 % )
    Info: Total interconnect delay = 6.067 ns ( 47.39 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 19%
    Info: The peak interconnect region extends from location X33_Y12 to location X43_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:11
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 70 output pins without output pin load capacitance assignment
    Info: Pin "psk_Q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q19" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q18" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q17" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q16" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q15" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q14" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q13" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q12" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q11" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q10" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "psk_I" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I19" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I18" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I17" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I16" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I15" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I14" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I13" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I12" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I11" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I10" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "enable" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ask_psk_mod" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "data_valid" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_I_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "wave_Q_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I115" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I114" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I113" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I112" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I111" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_I110" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q115" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q114" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q113" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q112" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q111" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "X_Q110" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 240 megabytes of memory during processing
    Info: Processing ended: Wed Aug 29 02:29:38 2007
    Info: Elapsed time: 00:01:03