📄 ask_dem_real.fit.rpt
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+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C35F672C7 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations ;
+----------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+------------------------------------------------------------------------------+------------------+
; Node ; Action ; Operation ; Reason ; Node Port ; Destination Node ; Destination Port ;
+----------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+------------------------------------------------------------------------------+------------------+
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_I1:inst|fir_I1_new:fir_I1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult1:inst6|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
; fir_Q1:inst16|fir_Q1_new:fir_Q1_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; lpm_mult0:inst2|lpm_mult:lpm_mult_component|mult_9ao:auto_generated|mac_out2 ; DATAOUT ;
+----------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+------------------------------------------------------------------------------+------------------+
+--------------+
; Pin-Out File ;
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