📄 constant32.vhd
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-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: constant32.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.1 Build 201 11/27/2006 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--lpm_constant CBX_AUTO_BLACKBOX="ON" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=1999999A LPM_WIDTH=32 result
--VERSION_BEGIN 6.1 cbx_lpm_constant 2006:01:26:12:27:46:SJ cbx_mgl 2006:10:27:16:08:48:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY constant32_lpm_constant_719 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END constant32_lpm_constant_719;
ARCHITECTURE RTL OF constant32_lpm_constant_719 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
BEGIN
result <= "00011001100110011001100110011010";
END RTL; --constant32_lpm_constant_719
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY constant32 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END constant32;
ARCHITECTURE RTL OF constant32 IS
ATTRIBUTE synthesis_clearbox: boolean;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT constant32_lpm_constant_719
PORT (
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
constant32_lpm_constant_719_component : constant32_lpm_constant_719
PORT MAP (
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: Value NUMERIC "429496730"
-- Retrieval info: PRIVATE: WIZMAN_OVERRIDE_CBX_GEN_MODE STRING "ON"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "429496730"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL constant32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL constant32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL constant32.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL constant32.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL constant32_inst.vhd FALSE
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