signal.map.qmsg

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 15:37:25 2008 " "Info: Processing started: Thu Apr 10 15:37:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off signal -c signal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signal -c signal" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file signal.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 signal " "Info: Found entity 1: signal" {  } { { "signal.bdf" "" { Schematic "D:/altera/quartus51/signal/signal.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "signal " "Info: Elaborating entity \"signal\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ram.v 1 1 " "Warning: Using design file ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram " "Info: Found entity 1: ram" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:inst " "Info: Elaborating entity \"ram\" for hierarchy \"ram:inst\"" {  } { { "signal.bdf" "inst" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 72 432 600 168 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sine.v 1 1 " "Warning: Using design file sine.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sine " "Info: Found entity 1: sine" {  } { { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sine sine:inst2 " "Info: Elaborating entity \"sine\" for hierarchy \"sine:inst2\"" {  } { { "signal.bdf" "inst2" { Schematic "D:/altera/quartus51/signal/signal.bdf" { { 72 216 344 168 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 sine.v(18) " "Warning (10230): Verilog HDL assignment warning at sine.v(18): truncated value with size 32 to match size of target (5)" {  } { { "sine.v" "" { Text "D:/altera/quartus51/signal/sine.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[10\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[10\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[10\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[10\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[9\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[9\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[9\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[9\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[8\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[8\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[8\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[8\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[7\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[7\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[6\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[6\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[5\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[5\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[4\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[4\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[3\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[3\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[3\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[3\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[2\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[2\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[2\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[1\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[1\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ram:inst\|memory\[0\]\[0\] High " "Info: Power-up level of register \"ram:inst\|memory\[0\]\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[0\]\[0\] data_in VCC " "Warning: Reduced register \"ram:inst\|memory\[0\]\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[1\]\[11\] data_in GND " "Warning: Reduced register \"ram:inst\|memory\[1\]\[11\]\" with stuck data_in port to stuck value GND" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[1\]\[10\] data_in GND " "Warning: Reduced register \"ram:inst\|memory\[1\]\[10\]\" with stuck data_in port to stuck value GND" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[1\]\[9\] data_in GND " "Warning: Reduced register \"ram:inst\|memory\[1\]\[9\]\" with stuck data_in port to stuck value GND" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ram:inst\|memory\[1\]\[8\] data_in GND " "Warning: Reduced register \"ram:inst\|memory\[1\]\[8\]\" with stuck data_in port to stuck value GND" {  } { { "ram.v" "" { Text "D:/altera/quartus51/signal/ram.v" 41 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}