signal.map.summary

产生sinx＋cosx波形 用于正交调制得测试信号 一次输出正交和同相分量 verilog语言

Analysis & Synthesis Status : Successful - Thu Apr 10 15:37:28 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : signal
Top-level Entity Name : signal
Family : Stratix
Total logic elements : 11
Total pins : 15
Total virtual pins : 0
Total memory bits : 320
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0