ctrl_doul_ram.v

Verilog语言实现的算端口模块（Dual_port_ram)

// read_wirte_ram.v
//11wolf  2007.11.09
module read_wirte_ram(clk,reset,ADDRA,ADDRB,RWA,RWB,BLKA,BLKB,CLKA,CLKB);

input  clk;
input  reset;
output CLKA,CLKB;             //两个端口的时钟
output BLKA,BLKB;             //两个端口A，B的使能,低有效
output RWA,RWB;              //读写混合信号，高电平读，低电平写
output [4:0] ADDRA,ADDRB;     //2个端口写入的地址

reg   [4:0] ADDRA,ADDRB;
reg   [7:0] DOUTA,DOUTB;
reg   BLKA,BLKB,RWA,RWB;
wire  CLKA,CLKB;
reg  [1:0] state;
assign CLKA=clk;             //读写时钟都为输入时钟48M
assign CLKB=clk;

parameter read = 2'b01,
          idle = 2'b10;



always @ (posedge clk)
  begin
   if(reset)
     begin
       ADDRA <=  5'd0;       //A口从地址0开始    
       ADDRB <=  5'd10;      //B口从地址10开始
       RWA   <=  1'b1;       //A、B读使能
       RWB   <=  1'b1;
       BLKA  <=  1'b0;       //使能AB端口
       BLKB  <=  1'b0;
       state <= read;
     end
   else 
     begin
       case(state)

        read: 
           begin
             ADDRA <= ADDRA + 1'b1;
             ADDRB <= ADDRB + 1'b1;
             if(ADDRA == 4'd9)
                begin
                  RWA   <=  1'b0;  //读禁止    
                  RWB   <=  1'b0;
                  state <=  idle;
                end
            end
         idle:
            begin
                state <=  idle;
            end
            

       endcase
     end
  end


 
endmodule