segatest.v

多功能数字时钟设计的源程序,可以实现计时闹钟鸣笛等基本功能.

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:17:42 01/18/2007
// Design Name:   seg7
// Module Name:   segatest.v
// Project Name:  sega
// Target Device:  
// Tool versions:  
// Description: 
 //
// Verilog Test Fixture created by ISE for module: seg7
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`include "segt.v"
module segatest_v;

	// Inputs
	reg clk;
	reg start,stop,clr;
	 
	// Outputs
	wire [3:0] an;
	wire [7:0] seg;

	// Instantiate the Unit Under Test (UUT)
	seg7 uut (
		.clk(clk), 
		.start(start),
		.stop(stop),
		.clr(clr), 
	
	);
	always #5 clk=~clk;
	initial begin
		// Initialize Inputs
		clk = 0;
		stop = 0;
		start=0;
		clr=1;
		

		// Wait 100 ns for global reset to finish
                #1000 clr=0;
		// Add stimulus here
		 #10 start=1;
		 
		 #400000000  stop=1;start=0;
		
		 #4000 clr=1;stop=0;
		 #20 clr=0;
		 #100 $finish ;
	end  
		 	 
endmodule