📄 decoder_3_to_8aa.rpt
字号:
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 6 B 12 OR2 ! 3 0 0 8 |DECODER_3_TO_8:17|:104
- 1 C 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:513
- 2 C 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:519
- 1 D 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:525
- 2 D 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:531
- 3 C 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:537
- 4 C 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:543
- 1 B 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:549
- 2 B 01 OR2 3 1 1 0 |DECODER_3_TO_8:17|:555
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register
Device-Specific Information: c:\max2work\decoder\decoder_3_to_8aa.rpt
decoder_3_to_8aa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/20( 10%) 0/20( 0%) 0/20( 0%)
B: 1/ 96( 1%) 4/ 48( 8%) 2/ 48( 4%) 2/20( 10%) 2/20( 10%) 0/20( 0%)
C: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 1/20( 5%) 4/20( 20%) 0/20( 0%)
D: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/20( 0%) 2/20( 10%) 0/20( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/20( 5%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\decoder\decoder_3_to_8aa.rpt
decoder_3_to_8aa
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
G1 : INPUT;
G2A : INPUT;
G2B : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC2_B1;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC1_B1;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC4_C1;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC3_C1;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC2_D1;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC1_D1;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC2_C1;
-- Node name is 'y7'
-- Equation name is 'y7', type is output
y7 = _LC1_C1;
-- Node name is '|DECODER_3_TO_8:17|:104'
-- Equation name is '_LC6_B12', type is buried
!_LC6_B12 = _LC6_B12~NOT;
_LC6_B12~NOT = LCELL( _EQ001);
_EQ001 = G2B
# G2A
# !G1;
-- Node name is '|DECODER_3_TO_8:17|:513'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ002);
_EQ002 = !_LC6_B12
# !C
# !B
# !A;
-- Node name is '|DECODER_3_TO_8:17|:519'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ003);
_EQ003 = !B
# !C
# A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:525'
-- Equation name is '_LC1_D1', type is buried
_LC1_D1 = LCELL( _EQ004);
_EQ004 = B
# !C
# !A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:531'
-- Equation name is '_LC2_D1', type is buried
_LC2_D1 = LCELL( _EQ005);
_EQ005 = B
# !C
# A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:537'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ006);
_EQ006 = !B
# C
# !A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:543'
-- Equation name is '_LC4_C1', type is buried
_LC4_C1 = LCELL( _EQ007);
_EQ007 = !B
# C
# A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:549'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ008);
_EQ008 = B
# C
# !A
# !_LC6_B12;
-- Node name is '|DECODER_3_TO_8:17|:555'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ009);
_EQ009 = B
# C
# A
# !_LC6_B12;
Project Information c:\max2work\decoder\decoder_3_to_8aa.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX6000' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,885K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -