count10.vhd

来自「一个十进制计数器的vhdl程序」· VHDL 代码 · 共 50 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT10 IS
    PORT (CLK : IN STD_LOGIC;                -- 时钟信号
        CLR : IN STD_LOGIC;                     -- 清零信号
        ENA : IN STD_LOGIC;                    -- 计数使能信号
        CNTQ : OUT INTEGER RANGE 0 TO 15;       -- 计数结果
        CNTOUT : OUT STD_LOGIC    );           -- 计数进位
   END COUNT10;
ARCHITECTURE A OF COUNT10 IS
    SIGNAL CNTI : INTEGER RANGE 0 TO 15;
BEGIN
    PROCESS(CLK, CLR, ENA)
      BEGIN
        IF CLR = '1' THEN   CNTI <= 0;             -- 清零
        ELSIF CLK'EVENT AND CLK = '1' THEN
            IF ENA = '1' THEN
                IF CNTI < 9 THEN   CNTI <= CNTI + 1;   
                  ELSE            CNTI <= 0;       -- 等于9，则回转
                END IF;
            END IF;
        END IF;
    END PROCESS;
    PROCESS(CNTI)
    BEGIN
        IF CNTI = 9 THEN CNTOUT <= '1';
        ELSE
            CNTOUT <= '0';
        END IF;
    END PROCESS;
    CNTQ <= CNTI;
END A;