mul_fix.v

来自「IEEE754 floating point mul」· Verilog 代码 · 共 51 行

/* ------------------------------------------------------------
// Module: MUL_Fix (Form: fix-point, for SM floating point)
// Edition: one
// Matlab code: None
// C code: None
// Architecture diagram: None 
// Date: 2008/01/30
// Update: 2008/01/30
// ------------------------------------------------------------ */



module MUL_Fix (In_x,In_y,Out);



/* ------------------------------------------------------------
// Parameters definition
// ------------------------------------------------------------ */

parameter DATA_WIDTH=50;	// bus width for data
	  
/* ------------------------------------------------------------
// I/O pin declaration
// ------------------------------------------------------------ */

input [DATA_WIDTH-1:0] In_x,In_y;			

output [DATA_WIDTH-1:0] Out; 		   

/* ------------------------------------------------------------
// Connection wire declaration
// ------------------------------------------------------------ */

wire [DATA_WIDTH-1:0] Out;

wire [2*DATA_WIDTH-2:0] mul_temp;


/* ------------------------------------------------------------
// Combinational logic
// ------------------------------------------------------------ */



assign mul_temp = In_x[DATA_WIDTH-1:0]*In_y[DATA_WIDTH-1:0];

assign Out=mul_temp[2*DATA_WIDTH-2:DATA_WIDTH-1];


endmodule