62256.tan.qmsg

EPM1270和ram62256的verilog接口程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_out\[1\] data_temp\[1\] 13.159 ns register " "Info: tco from clock \"clk\" to destination pin \"data_out\[1\]\" through register \"data_temp\[1\]\" is 13.159 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.993 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns read 2 REG LC_X2_Y3_N7 9 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 9; REG Node = 'read'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk read } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.758 ns) + CELL(0.511 ns) 7.993 ns data_temp\[1\] 3 REG LC_X7_Y4_N6 1 " "Info: 3: + IC(3.758 ns) + CELL(0.511 ns) = 7.993 ns; Loc. = LC_X7_Y4_N6; Fanout = 1; REG Node = 'data_temp\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.269 ns" { read data_temp[1] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.968 ns ( 37.13 % ) " "Info: Total cell delay = 2.968 ns ( 37.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.025 ns ( 62.87 % ) " "Info: Total interconnect delay = 5.025 ns ( 62.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.993 ns" { clk read data_temp[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.993 ns" { clk clk~combout read data_temp[1] } { 0.000ns 0.000ns 1.267ns 3.758ns } { 0.000ns 1.163ns 1.294ns 0.511ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.166 ns + Longest register pin " "Info: + Longest register to pin delay is 5.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_temp\[1\] 1 REG LC_X7_Y4_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N6; Fanout = 1; REG Node = 'data_temp\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_temp[1] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 0.505 ns data_out~81 2 COMB LC_X7_Y4_N7 1 " "Info: 2: + IC(0.305 ns) + CELL(0.200 ns) = 0.505 ns; Loc. = LC_X7_Y4_N7; Fanout = 1; COMB Node = 'data_out~81'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { data_temp[1] data_out~81 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.339 ns) + CELL(2.322 ns) 5.166 ns data_out\[1\] 3 PIN PIN_4 0 " "Info: 3: + IC(2.339 ns) + CELL(2.322 ns) = 5.166 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'data_out\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.661 ns" { data_out~81 data_out[1] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 48.82 % ) " "Info: Total cell delay = 2.522 ns ( 48.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.644 ns ( 51.18 % ) " "Info: Total interconnect delay = 2.644 ns ( 51.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.166 ns" { data_temp[1] data_out~81 data_out[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.166 ns" { data_temp[1] data_out~81 data_out[1] } { 0.000ns 0.305ns 2.339ns } { 0.000ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.993 ns" { clk read data_temp[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.993 ns" { clk clk~combout read data_temp[1] } { 0.000ns 0.000ns 1.267ns 3.758ns } { 0.000ns 1.163ns 1.294ns 0.511ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.166 ns" { data_temp[1] data_out~81 data_out[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.166 ns" { data_temp[1] data_out~81 data_out[1] } { 0.000ns 0.305ns 2.339ns } { 0.000ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data_in\[4\] data_io\[4\] 6.495 ns Longest " "Info: Longest tpd from source pin \"data_in\[4\]\" to destination pin \"data_io\[4\]\" is 6.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns data_in\[4\] 1 PIN PIN_75 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_75; Fanout = 2; PIN Node = 'data_in\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_in[4] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.041 ns) + CELL(2.322 ns) 6.495 ns data_io\[4\] 2 PIN PIN_76 0 " "Info: 2: + IC(3.041 ns) + CELL(2.322 ns) = 6.495 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'data_io\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.363 ns" { data_in[4] data_io[4] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 53.18 % ) " "Info: Total cell delay = 3.454 ns ( 53.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.041 ns ( 46.82 % ) " "Info: Total interconnect delay = 3.041 ns ( 46.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.495 ns" { data_in[4] data_io[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.495 ns" { data_in[4] data_in[4]~combout data_io[4] } { 0.000ns 0.000ns 3.041ns } { 0.000ns 1.132ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data_temp\[3\] data_io\[3\] clk 2.724 ns register " "Info: th for register \"data_temp\[3\]\" (data pin = \"data_io\[3\]\", clock pin = \"clk\") is 2.724 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.003 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns read 2 REG LC_X2_Y3_N7 9 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 9; REG Node = 'read'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk read } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.768 ns) + CELL(0.511 ns) 8.003 ns data_temp\[3\] 3 REG LC_X7_Y4_N1 1 " "Info: 3: + IC(3.768 ns) + CELL(0.511 ns) = 8.003 ns; Loc. = LC_X7_Y4_N1; Fanout = 1; REG Node = 'data_temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.279 ns" { read data_temp[3] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.968 ns ( 37.09 % ) " "Info: Total cell delay = 2.968 ns ( 37.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.035 ns ( 62.91 % ) " "Info: Total interconnect delay = 5.035 ns ( 62.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.003 ns" { clk read data_temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.003 ns" { clk clk~combout read data_temp[3] } { 0.000ns 0.000ns 1.267ns 3.768ns } { 0.000ns 1.163ns 1.294ns 0.511ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.279 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_io\[3\] 1 PIN PIN_72 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_72; Fanout = 1; PIN Node = 'data_io\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_io[3] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns data_io\[3\]~4 2 COMB IOC_X8_Y4_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X8_Y4_N2; Fanout = 1; COMB Node = 'data_io\[3\]~4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.132 ns" { data_io[3] data_io[3]~4 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.407 ns) + CELL(0.740 ns) 5.279 ns data_temp\[3\] 3 REG LC_X7_Y4_N1 1 " "Info: 3: + IC(3.407 ns) + CELL(0.740 ns) = 5.279 ns; Loc. = LC_X7_Y4_N1; Fanout = 1; REG Node = 'data_temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.147 ns" { data_io[3]~4 data_temp[3] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.872 ns ( 35.46 % ) " "Info: Total cell delay = 1.872 ns ( 35.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.407 ns ( 64.54 % ) " "Info: Total interconnect delay = 3.407 ns ( 64.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.279 ns" { data_io[3] data_io[3]~4 data_temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.279 ns" { data_io[3] data_io[3]~4 data_temp[3] } { 0.000ns 0.000ns 3.407ns } { 0.000ns 1.132ns 0.740ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.003 ns" { clk read data_temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.003 ns" { clk clk~combout read data_temp[3] } { 0.000ns 0.000ns 1.267ns 3.768ns } { 0.000ns 1.163ns 1.294ns 0.511ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.279 ns" { data_io[3] data_io[3]~4 data_temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.279 ns" { data_io[3] data_io[3]~4 data_temp[3] } { 0.000ns 0.000ns 3.407ns } { 0.000ns 1.132ns 0.740ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 29 20:13:27 2007 " "Info: Processing ended: Sun Jul 29 20:13:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}