62256.tan.qmsg

EPM1270和ram62256的verilog接口程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[0\] " "Warning: Node \"data_temp\[0\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[1\] " "Warning: Node \"data_temp\[1\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[2\] " "Warning: Node \"data_temp\[2\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[3\] " "Warning: Node \"data_temp\[3\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[4\] " "Warning: Node \"data_temp\[4\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[5\] " "Warning: Node \"data_temp\[5\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[6\] " "Warning: Node \"data_temp\[6\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_temp\[7\] " "Warning: Node \"data_temp\[7\]\" is a latch" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 57 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "read " "Info: Detected ripple clock \"read\" as buffer" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 49 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "read" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register addr\[9\]~reg0 register addr\[5\]~reg0 84.59 MHz 11.822 ns Internal " "Info: Clock \"clk\" has Internal fmax of 84.59 MHz between source register \"addr\[9\]~reg0\" and destination register \"addr\[5\]~reg0\" (period= 11.822 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.113 ns + Longest register register " "Info: + Longest register to register delay is 11.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr\[9\]~reg0 1 REG LC_X5_Y2_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'addr\[9\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr[9]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.228 ns) + CELL(0.200 ns) 3.428 ns Equal1~188 2 COMB LC_X5_Y3_N1 1 " "Info: 2: + IC(3.228 ns) + CELL(0.200 ns) = 3.428 ns; Loc. = LC_X5_Y3_N1; Fanout = 1; COMB Node = 'Equal1~188'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.428 ns" { addr[9]~reg0 Equal1~188 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.933 ns Equal1~189 3 COMB LC_X5_Y3_N2 2 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.933 ns; Loc. = LC_X5_Y3_N2; Fanout = 2; COMB Node = 'Equal1~189'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal1~188 Equal1~189 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.200 ns) 5.279 ns Equal0~131 4 COMB LC_X6_Y3_N8 6 " "Info: 4: + IC(1.146 ns) + CELL(0.200 ns) = 5.279 ns; Loc. = LC_X6_Y3_N8; Fanout = 6; COMB Node = 'Equal0~131'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.346 ns" { Equal1~189 Equal0~131 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.200 ns) 6.201 ns addr\[7\]~1362 5 COMB LC_X6_Y3_N4 3 " "Info: 5: + IC(0.722 ns) + CELL(0.200 ns) = 6.201 ns; Loc. = LC_X6_Y3_N4; Fanout = 3; COMB Node = 'addr\[7\]~1362'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.922 ns" { Equal0~131 addr[7]~1362 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.972 ns) + CELL(0.511 ns) 8.684 ns addr\[7\]~1363 6 COMB LC_X3_Y3_N7 8 " "Info: 6: + IC(1.972 ns) + CELL(0.511 ns) = 8.684 ns; Loc. = LC_X3_Y3_N7; Fanout = 8; COMB Node = 'addr\[7\]~1363'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.483 ns" { addr[7]~1362 addr[7]~1363 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.838 ns) + CELL(0.591 ns) 11.113 ns addr\[5\]~reg0 7 REG LC_X6_Y3_N1 6 " "Info: 7: + IC(1.838 ns) + CELL(0.591 ns) = 11.113 ns; Loc. = LC_X6_Y3_N1; Fanout = 6; REG Node = 'addr\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.429 ns" { addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.902 ns ( 17.12 % ) " "Info: Total cell delay = 1.902 ns ( 17.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.211 ns ( 82.88 % ) " "Info: Total interconnect delay = 9.211 ns ( 82.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.113 ns" { addr[9]~reg0 Equal1~188 Equal1~189 Equal0~131 addr[7]~1362 addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.113 ns" { addr[9]~reg0 Equal1~188 Equal1~189 Equal0~131 addr[7]~1362 addr[7]~1363 addr[5]~reg0 } { 0.000ns 3.228ns 0.305ns 1.146ns 0.722ns 1.972ns 1.838ns } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.511ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns addr\[5\]~reg0 2 REG LC_X6_Y3_N1 6 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y3_N1; Fanout = 6; REG Node = 'addr\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns addr\[9\]~reg0 2 REG LC_X5_Y2_N9 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'addr\[9\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk addr[9]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[9]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[9]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[9]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[9]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.113 ns" { addr[9]~reg0 Equal1~188 Equal1~189 Equal0~131 addr[7]~1362 addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.113 ns" { addr[9]~reg0 Equal1~188 Equal1~189 Equal0~131 addr[7]~1362 addr[7]~1363 addr[5]~reg0 } { 0.000ns 3.228ns 0.305ns 1.146ns 0.722ns 1.972ns 1.838ns } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.511ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[9]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[9]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "addr\[5\]~reg0 addr_in\[1\] clk 11.210 ns register " "Info: tsu for register \"addr\[5\]~reg0\" (data pin = \"addr_in\[1\]\", clock pin = \"clk\") is 11.210 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.225 ns + Longest pin register " "Info: + Longest pin to register delay is 14.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns addr_in\[1\] 1 PIN PIN_12 5 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 5; PIN Node = 'addr_in\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr_in[1] } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.944 ns) + CELL(0.978 ns) 4.085 ns Add1~125 2 COMB LC_X4_Y3_N1 2 " "Info: 2: + IC(1.944 ns) + CELL(0.978 ns) = 4.085 ns; Loc. = LC_X4_Y3_N1; Fanout = 2; COMB Node = 'Add1~125'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.922 ns" { addr_in[1] Add1~125 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 4.208 ns Add1~115 3 COMB LC_X4_Y3_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 4.208 ns; Loc. = LC_X4_Y3_N2; Fanout = 2; COMB Node = 'Add1~115'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { Add1~125 Add1~115 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 5.023 ns Add1~118 4 COMB LC_X4_Y3_N3 1 " "Info: 4: + IC(0.000 ns) + CELL(0.815 ns) = 5.023 ns; Loc. = LC_X4_Y3_N3; Fanout = 1; COMB Node = 'Add1~118'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.815 ns" { Add1~115 Add1~118 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.769 ns) + CELL(0.200 ns) 6.992 ns Equal1~191 5 COMB LC_X4_Y2_N2 1 " "Info: 5: + IC(1.769 ns) + CELL(0.200 ns) = 6.992 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Equal1~191'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.969 ns" { Add1~118 Equal1~191 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.511 ns) 9.345 ns Equal1~195 6 COMB LC_X5_Y3_N4 6 " "Info: 6: + IC(1.842 ns) + CELL(0.511 ns) = 9.345 ns; Loc. = LC_X5_Y3_N4; Fanout = 6; COMB Node = 'Equal1~195'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.353 ns" { Equal1~191 Equal1~195 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.746 ns) + CELL(0.200 ns) 11.291 ns addr\[7\]~1384 7 COMB LC_X3_Y3_N6 1 " "Info: 7: + IC(1.746 ns) + CELL(0.200 ns) = 11.291 ns; Loc. = LC_X3_Y3_N6; Fanout = 1; COMB Node = 'addr\[7\]~1384'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.946 ns" { Equal1~195 addr[7]~1384 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 11.796 ns addr\[7\]~1363 8 COMB LC_X3_Y3_N7 8 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 11.796 ns; Loc. = LC_X3_Y3_N7; Fanout = 8; COMB Node = 'addr\[7\]~1363'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { addr[7]~1384 addr[7]~1363 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.838 ns) + CELL(0.591 ns) 14.225 ns addr\[5\]~reg0 9 REG LC_X6_Y3_N1 6 " "Info: 9: + IC(1.838 ns) + CELL(0.591 ns) = 14.225 ns; Loc. = LC_X6_Y3_N1; Fanout = 6; REG Node = 'addr\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.429 ns" { addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.781 ns ( 33.61 % ) " "Info: Total cell delay = 4.781 ns ( 33.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.444 ns ( 66.39 % ) " "Info: Total interconnect delay = 9.444 ns ( 66.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.225 ns" { addr_in[1] Add1~125 Add1~115 Add1~118 Equal1~191 Equal1~195 addr[7]~1384 addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.225 ns" { addr_in[1] addr_in[1]~combout Add1~125 Add1~115 Add1~118 Equal1~191 Equal1~195 addr[7]~1384 addr[7]~1363 addr[5]~reg0 } { 0.000ns 0.000ns 1.944ns 0.000ns 0.000ns 1.769ns 1.842ns 1.746ns 0.305ns 1.838ns } { 0.000ns 1.163ns 0.978ns 0.123ns 0.815ns 0.200ns 0.511ns 0.200ns 0.200ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns addr\[5\]~reg0 2 REG LC_X6_Y3_N1 6 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y3_N1; Fanout = 6; REG Node = 'addr\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "inter62256.v" "" { Text "E:/电子设计竞赛/verilog/62256接口/inter62256.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.225 ns" { addr_in[1] Add1~125 Add1~115 Add1~118 Equal1~191 Equal1~195 addr[7]~1384 addr[7]~1363 addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.225 ns" { addr_in[1] addr_in[1]~combout Add1~125 Add1~115 Add1~118 Equal1~191 Equal1~195 addr[7]~1384 addr[7]~1363 addr[5]~reg0 } { 0.000ns 0.000ns 1.944ns 0.000ns 0.000ns 1.769ns 1.842ns 1.746ns 0.305ns 1.838ns } { 0.000ns 1.163ns 0.978ns 0.123ns 0.815ns 0.200ns 0.511ns 0.200ns 0.200ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout addr[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}