inter62256.v.bak

EPM1270和ram62256的verilog接口程序

module inter62256(
clk,
rst,
CS,
OE,
WE,
addr,
data_io,
addr_in,

read_en,
write_en,
write_clk,
data_in,
data_out,
req,
mode
);

input clk;
input rst;
output CS;
output OE;
output WE;
output[14:0] addr;
inout [7:0]  data_io;
input mode;  //模式：0经过RAM，1不经过RAM

input [7:0]  addr_in; //输入偏移地址0～200
input read_en;
input write_en;  //要在write_clk的下降沿上升，保证第一个数能写入
input write_clk; //写时钟，接受到一个write_en脉冲后开始写，低电平读入数据
input [7:0] data_in;
output[7:0] data_out;
output req;  //向单片机发出读取请求

reg CS;
reg OE;
reg WE;
reg[1:0] WE_hold;
reg drop;//用来把写的第一个时钟去掉
reg write_en0;
reg write_en1;
reg read_en0;
reg read_en1;
reg write_clk0;
reg write_clk1;
reg req;
reg read;  //接口读
reg write; //接口写
reg mod; //模式0：与data_temp相连；模式1：与data_in相连
reg wr; //读写标志位，0读，1写
reg [14:0]  addr;
//reg [7:0]   addr_cnt; //读数据地址计数器，0～250
reg [7:0]   data_in_temp; //data_in的寄存器
wire[7:0]   data_out;//模式0：与data_temp相连；模式1：与data_in相连
wire[7:0]   data_temp; //实现模式转换时，data_out的转接

always @(posedge clk)
begin
  if(rst <= 1'b0)
  begin
    read <= 1'b0;
    write <= 1'b0;
    addr <= 15'b0;
    wr <= 1'b0;
    write_en0 <= 1'b0;
    write_en1 <= 1'b0;
    read_en0 <= 1'b0;
    read_en1 <= 1'b0;
    write_clk0 <= 1'b0;
    write_clk1 <= 1'b0;
    req <= 1'b0;
    CS <= 1'b1;
    OE <= 1'b1;
    WE <= 1'b1;
    WE_hold <= 2'b0;
    drop  <= 1'b0;
  end
  else
  begin
    CS <= 1'b0;
    write_en0 <= write_en;
    write_en1 <= write_en0;
    read_en0 <= read_en;
    read_en1 <= read_en0;
    write_clk0 <= write_clk;
    write_clk1 <= write_clk0;

    if( mode == 1'b0 )
/////////////////////////////////////////////////////////
    begin
    mod <= 1'b0;
    
    if( write_en0 == 1'b1 && write_en1 == 1'b0 ) //上升沿
    begin
      wr <= 1'b1;  //开始写
      WE <= 1'b0;
      read <= 1'b0; 
      write <= 1'b1;  //打开数据口，开始输出数据
      addr <= 15'b0;
      drop <= 1'b0;
      req <= 1'b0;  //读完250个数，请求停止
    end

    if( wr == 1'b1 ) //写过程
    begin
      if( write_clk0 == 1'b0 && write_clk1 == 1'b1 ) //下降沿
      begin
        drop <= 1'b1;
      end

      if( write_clk0 == 1'b0 && write_clk1 == 1'b1 && drop == 1'b1 ) //下降沿
      begin
        WE <= 1'b1;  //数据写入
        WE_hold[0] <= 1'b1;
      end
      
      if( WE_hold[0] == 1'b1 ) //WE保持2个晶振周期
      begin
        WE_hold[0] <= 1'b0;
        WE_hold[1] <= 1'b1;
        addr <= addr + 15'b1;  //地址更新
      end
      
      if( WE_hold[1] == 1'b1 ) //下一次写入开始
      begin
        WE <= 1'b0;
        WE_hold <= 2'b0;
      end

      if( addr == 500) //采集500个数就停止，开始读过程
      begin
        wr <= 1'b0;
        write <= 1'b0; //输出口变为高阻态
        read <= 1'b0;
        req <= 1'b1;  //读请求
        addr <= {6'b0,addr_in}; //
        OE <= 1'b1;
      end
    end

    if( wr == 1'b0 )   //读过程
    begin
      if( read_en0 == 1'b1 && read_en1 == 1'b0 ) //上升沿
      begin
        OE <= 1'b0;
        read <= 1'b1;  //打开数据口，输入
      end
      
      if( read_en0 == 1'b0 && read_en1 == 1'b1 ) //下降沿
      begin
        addr <= addr + 15'b1;  //地址更新
        OE <= 1'b1;
        read <= 1'b0;  //数据锁住，保持上一个数据
      end

      if( addr == addr_in + 250)
      begin
        req <= 1'b0;  //读完250个数，请求停止
        addr <= 15'b0;
        OE <= 1'b1;
      end
    end
    end
/////////////////////////////////////////////////////////
    else
    begin
      mod <= 1'b1;
      if( write_clk0 == 1'b0 && write_clk1 == 1'b1 ) //下降沿
      begin
        data_in_temp <= data_in;
        req <= 1'b1;
      end
      
      if( read_en0 == 1'b1 && read_en1 == 1'b0 ) //上升沿
      begin
        req <= 1'b0;
      end
    end

  end
end

assign  data_io = write ? data_in : 8'bzzzzzzzz;
assign  data_temp = read ? data_io : data_temp;
assign  data_out = mod ? data_in_temp : data_temp;
endmodule