62256.map.rpt

EPM1270和ram62256的verilog接口程序

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 114   ;
;     -- Combinational with no register       ; 75    ;
;     -- Register only                        ; 9     ;
;     -- Combinational with a register        ; 30    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 39    ;
;     -- 3 input functions                    ; 24    ;
;     -- 2 input functions                    ; 39    ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 94    ;
;     -- arithmetic mode                      ; 20    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 6     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 39    ;
; Total logic cells in carry chains           ; 22    ;
; I/O pins                                    ; 57    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 39    ;
; Total fan-out                               ; 433   ;
; Average fan-out                             ; 2.53  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |inter62256                ; 114 (114)   ; 39           ; 0          ; 57   ; 0            ; 75 (75)      ; 9 (9)             ; 30 (30)          ; 22 (22)         ; 0 (0)      ; |inter62256         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; data_temp[0]                                       ; read                ; yes                    ;
; data_temp[1]                                       ; read                ; yes                    ;
; data_temp[2]                                       ; read                ; yes                    ;
; data_temp[3]                                       ; read                ; yes                    ;
; data_temp[4]                                       ; read                ; yes                    ;
; data_temp[5]                                       ; read                ; yes                    ;
; data_temp[6]                                       ; read                ; yes                    ;
; data_temp[7]                                       ; read                ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 39    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 27    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 8:1                ; 7 bits    ; 35 LEs        ; 7 LEs                ; 28 LEs                 ; Yes        ; |inter62256|addr[9]~reg0   ;
; 8:1                ; 8 bits    ; 40 LEs        ; 16 LEs               ; 24 LEs                 ; Yes        ; |inter62256|addr[7]~reg0   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jul 29 20:13:07 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 62256 -c 62256
Info: Found 1 design units, including 1 entities, in source file inter62256.v
    Info: Found entity 1: inter62256
Info: Elaborating entity "inter62256" for the top level hierarchy
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[7]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[6]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[5]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[4]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[3]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[2]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[1]"
Info (10041): Verilog HDL or VHDL info at inter62256.v(57): inferred latch for "data_temp[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "wr" merged to single register "write"
Info: Implemented 171 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 27 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 114 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Jul 29 20:13:11 2007
    Info: Elapsed time: 00:00:05